From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 29 Jun 2019 09:33:28 +0000 (+0100)
Subject: comments
X-Git-Tag: ls180-24jan2020~957
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0087cc199190a70fbd612651b738ff4e9c0e21d5;p=ieee754fpu.git

comments
---

diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 167edde6..0667639d 100644
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -64,6 +64,10 @@ class FPDivStage0Mod(Elaboratable):
         # *begins* the processing phase (enters the massive DIV
         # pipeline chain) - see ospec.
 
+        # NOTE: this stage does *NOT* do *ACTUAL* DIV processing,
+        # it is PURELY the *ENTRY* point into the chain, performing
+        # "preparation" work
+
         # store intermediate tests (and zero-extended mantissas)
         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
diff --git a/src/ieee754/fpdiv/div2.py b/src/ieee754/fpdiv/div2.py
index 6b9be39c..1b54db47 100644
--- a/src/ieee754/fpdiv/div2.py
+++ b/src/ieee754/fpdiv/div2.py
@@ -50,6 +50,9 @@ class FPDivStage2Mod(FPState, Elaboratable):
         # last-stage guard/round/sticky and copies mantissa into z.
         # post-processing stages take care of things from that point.
 
+        # NOTE: this phase does NOT do ACTUAL DIV processing, it ONLY
+        # does "conversion" *out* of the Q/REM last stage
+
         with m.If(~self.i.out_do_z):
             mw = self.o.z.m_width
             m.d.comb += [