From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 17 Jan 2020 12:17:08 +0000 (+0100)
Subject: targets/nexys4ddr: fix typo
X-Git-Tag: 24jan2021_ls180~729
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=008a0894719f6365bacd433b9f33e90c33e14783;p=litex.git

targets/nexys4ddr: fix typo
---

diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index b4a4494c..8940ac4a 100755
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -79,7 +79,7 @@ class EthernetSoC(BaseSoC):
 
         # Ethernet ---------------------------------------------------------------------------------
         # phy
-        self.submodules.ethphy = LiteEthPHYMII(
+        self.submodules.ethphy = LiteEthPHYRMII(
             clock_pads = self.platform.request("eth_clocks"),
             pads       = self.platform.request("eth"))
         self.add_csr("ethphy")