From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 6 Nov 2023 02:14:29 +0000 (-0800)
Subject: log load/stores to InstrInOuts
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=008a330c04a63f0fb7281e36970f686d11e64eb5;p=openpower-isa.git

log load/stores to InstrInOuts
---

diff --git a/src/openpower/decoder/isa/mem.py b/src/openpower/decoder/isa/mem.py
index ebd86bb8..7b8c2dda 100644
--- a/src/openpower/decoder/isa/mem.py
+++ b/src/openpower/decoder/isa/mem.py
@@ -199,11 +199,11 @@ class MemCommon:
 
     def __call__(self, addr, sz):
         val = self.ld(addr.value, sz, swap=False)
-        log("memread", addr, sz, val)
+        log("memread", addr, sz, hex(val), kind=LogType.InstrInOuts)
         return SelectableInt(val, sz*8)
 
     def memassign(self, addr, sz, val):
-        log("memassign", addr, sz, val)
+        log("memassign", addr, sz, val, kind=LogType.InstrInOuts)
         self.st(addr.value, val.value, sz, swap=False)
 
     def dump(self, printout=True, asciidump=False):