From: lkcl <lkcl@web>
Date: Sun, 4 Sep 2022 12:42:17 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~706
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=00abecc6f56ea2be339bfb56e50894f0915ca2a7;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 2b430f931..548b9707f 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -94,6 +94,24 @@ Comparative instruction count:
   SFFS (214) Compliancy Subsets.
   **There are no dedicated Vector instructions, only Scalar-prefixed**.
 
+Comparative Basic Design Principle:
+
+* ARM NEON and VSX: PackedSIMD. No instruction-overloaded meaning
+  (every instruction is unique for a given register bitwidth,
+  guaranteeing binary interoperability)
+* Intel AVX-512 (and below): Hybrid Packed-Predicated SIMD with no
+  instruction-overloading, guaranteeing binary interoperability
+* ARM SVE/SVE2: Hybrid Packed-Predicated SIMD with instruction-overloading
+  that destroys binary interoperability. This is hidden behind the
+  misuse of the word "Scalable".
+* RISC-V RVV: Cray-style Scalable Vector but with instruction-overloading
+  that destroys binary interoperability.
+* SVP64: Cray-style Scalable Vector with no instruction-overloaded
+  meanings.  The regfile numbers and bitwidths shall **not** change
+  in a future revision: "Silicon Partner" Scaling is prohibited,
+  in order to guarantee binary interoperability.  Future revisions
+  of SVP64 will extend VSX to achieve larger regfiles.
+
 SV comprises several [[sv/compliancy_levels]] suited to Embedded, Energy
 efficient High-Performance Compute, Distributed Computing and Advanced
 Computational Supercomputing.  The Compliancy Levels are arranged such