From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 25 May 2020 23:40:53 +0000 (-0700)
Subject: abc9_ops: -prep_xaiger exclude (* abc9_keep *) wires from toposort
X-Git-Tag: working-ls180~512^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=00c5ceb1f2c28435fa245a5183d325c441b8e5eb;p=yosys.git

abc9_ops: -prep_xaiger exclude (* abc9_keep *) wires from toposort
---

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 8d55b18a0..16b468b19 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -719,8 +719,10 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 					bit_users[bit].insert(cell->name);
 
 			if (cell->output(conn.first) && !abc9_flop)
-				for (auto bit : sigmap(conn.second))
-					bit_drivers[bit].insert(cell->name);
+				for (const auto &chunk : conn.second.chunks())
+				    if (!chunk.wire->get_bool_attribute(ID::abc9_keep))
+					    for (auto b : sigmap(SigSpec(chunk)))
+						    bit_drivers[b].insert(cell->name);
 		}
 		toposort.node(cell->name);
 	}