From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 20 Aug 2019 05:56:19 +0000 (+0100)
Subject: update comments
X-Git-Tag: ls180-24jan2020~468
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=00c68305374c9a8a11de9ae4d5e974a3f49a68b9;p=ieee754fpu.git

update comments
---

diff --git a/src/ieee754/part_mul_add/multiply.py b/src/ieee754/part_mul_add/multiply.py
index 820133a1..4c3a3cf1 100644
--- a/src/ieee754/part_mul_add/multiply.py
+++ b/src/ieee754/part_mul_add/multiply.py
@@ -395,8 +395,9 @@ class AddReduce(Elaboratable):
             m.d.comb += adder_i.in1.eq(self._resized_inputs[i + 1])
             m.d.comb += adder_i.in2.eq(self._resized_inputs[i + 2])
             m.d.comb += adder_i.mask.eq(part_mask)
+            # add both the sum and the masked-carry to the next level.
+            # 3 inputs have now been reduced to 2...
             add_intermediate_term(adder_i.sum)
-            # mask out carry bits to prevent carries between partitions
             add_intermediate_term(adder_i.mcarry)
         # handle the remaining inputs.
         if len(self.inputs) % FULL_ADDER_INPUT_COUNT == 1: