From: Julian Brown Date: Fri, 30 Jun 2017 03:58:48 +0000 (+0000) Subject: aarch64-fusion-pairs.def: Add ALU_BRANCH entry. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=00c7c57f0df9b416f7f2eec88717c526d80196e3;p=gcc.git aarch64-fusion-pairs.def: Add ALU_BRANCH entry. 2017-06-29 Julian Brown Naveen H.S * config/aarch64/aarch64-fusion-pairs.def: Add ALU_BRANCH entry. * config/aarch64/aarch64.c (AARCH64_FUSE_ALU_BRANCH): New fusion type. (thunderx2t99_tunings): Set AARCH64_FUSE_ALU_BRANCH flag. (aarch_macro_fusion_pair_p): Add support for AARCH64_FUSE_ALU_BRANCH. Co-Authored-By: Naveen H.S From-SVN: r249828 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2c57178ef27..f66b41ef484 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2017-06-29 Julian Brown + Naveen H.S + + * config/aarch64/aarch64-fusion-pairs.def: Add ALU_BRANCH entry. + * config/aarch64/aarch64.c (AARCH64_FUSE_ALU_BRANCH): New fusion type. + (thunderx2t99_tunings): Set AARCH64_FUSE_ALU_BRANCH flag. + (aarch_macro_fusion_pair_p): Add support for AARCH64_FUSE_ALU_BRANCH. + 2017-06-29 Naveen H.S * config/aarch64/aarch64.c (aarch_macro_fusion_pair_p): Push the diff --git a/gcc/config/aarch64/aarch64-fusion-pairs.def b/gcc/config/aarch64/aarch64-fusion-pairs.def index f0e6dbcdd81..300cd00e4bf 100644 --- a/gcc/config/aarch64/aarch64-fusion-pairs.def +++ b/gcc/config/aarch64/aarch64-fusion-pairs.def @@ -34,5 +34,6 @@ AARCH64_FUSION_PAIR ("movk+movk", MOVK_MOVK) AARCH64_FUSION_PAIR ("adrp+ldr", ADRP_LDR) AARCH64_FUSION_PAIR ("cmp+branch", CMP_BRANCH) AARCH64_FUSION_PAIR ("aes+aesmc", AES_AESMC) +AARCH64_FUSION_PAIR ("alu+branch", ALU_BRANCH) #undef AARCH64_FUSION_PAIR diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index b8ce5af1592..037339d431d 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -875,7 +875,8 @@ static const struct tune_params thunderx2t99_tunings = &generic_approx_modes, 4, /* memmov_cost. */ 4, /* issue_rate. */ - (AARCH64_FUSE_CMP_BRANCH | AARCH64_FUSE_AES_AESMC), /* fusible_ops */ + (AARCH64_FUSE_CMP_BRANCH | AARCH64_FUSE_AES_AESMC + | AARCH64_FUSE_ALU_BRANCH), /* fusible_ops */ 16, /* function_align. */ 8, /* jump_align. */ 16, /* loop_align. */ @@ -14323,6 +14324,49 @@ aarch_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr) } } + if (aarch64_fusion_enabled_p (AARCH64_FUSE_ALU_BRANCH) + && any_condjump_p (curr)) + { + /* We're trying to match: + prev (alu_insn) == (set (r0) plus ((r0) (r1/imm))) + curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0) + (const_int 0)) + (label_ref ("SYM")) + (pc)) */ + if (SET_DEST (curr_set) == (pc_rtx) + && GET_CODE (SET_SRC (curr_set)) == IF_THEN_ELSE + && REG_P (XEXP (XEXP (SET_SRC (curr_set), 0), 0)) + && REG_P (SET_DEST (prev_set)) + && REGNO (SET_DEST (prev_set)) + == REGNO (XEXP (XEXP (SET_SRC (curr_set), 0), 0))) + { + /* Fuse ALU operations followed by conditional branch instruction. */ + switch (get_attr_type (prev)) + { + case TYPE_ALU_IMM: + case TYPE_ALU_SREG: + case TYPE_ADC_REG: + case TYPE_ADC_IMM: + case TYPE_ADCS_REG: + case TYPE_ADCS_IMM: + case TYPE_LOGIC_REG: + case TYPE_LOGIC_IMM: + case TYPE_CSEL: + case TYPE_ADR: + case TYPE_MOV_IMM: + case TYPE_SHIFT_REG: + case TYPE_SHIFT_IMM: + case TYPE_BFM: + case TYPE_RBIT: + case TYPE_REV: + case TYPE_EXTEND: + return true; + + default:; + } + } + } + return false; }