From: Alberto Gonzalez <boqwxp@airmail.cc>
Date: Fri, 17 Apr 2020 06:23:03 +0000 (+0000)
Subject: Set Verilog source location for explicit blocks (`begin` ... `end`).
X-Git-Tag: working-ls180~619^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=00d74f0b9ceecc7b60f50fddb3b6ab0c47701923;p=yosys.git

Set Verilog source location for explicit blocks (`begin` ... `end`).
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index f762f9025..4a5aba79e 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -2246,6 +2246,7 @@ behavioral_stmt:
 		exitTypeScope();
 		if ($4 != NULL && $8 != NULL && *$4 != *$8)
 			frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1);
+		SET_AST_NODE_LOC(ast_stack.back(), @2, @8);
 		delete $4;
 		delete $8;
 		ast_stack.pop_back();