From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 29 Jan 2022 10:17:42 +0000 (+0000)
Subject: bug in dcache.py where when two stores occur in the same real page
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=00e741a5d4f356fd70807bde12e8778a3448e75e;p=soc.git

bug in dcache.py where when two stores occur in the same real page
the address is corrupted.
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 0d021e0d..eb8b8bf9 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1639,7 +1639,7 @@ class DCache(Elaboratable):
                     # See if there is another store waiting
                     # to be done which is in the same real page.
                     with m.If(req.valid):
-                        _ra = req.real_addr[ROW_LINE_BITS:SET_SIZE_BITS]
+                        _ra = req.real_addr[0:SET_SIZE_BITS]
                         sync += r1.wb.adr[0:SET_SIZE_BITS].eq(_ra)
                         sync += r1.wb.dat.eq(req.data)
                         sync += r1.wb.sel.eq(req.byte_sel)