From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 27 Jun 2019 23:13:22 +0000 (-0700)
Subject: Reduce diff with upstream
X-Git-Tag: working-ls180~1237^2~7
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=00f63d82ce4fbaa0f63ff2c68d4941f7eb16dfc4;p=yosys.git

Reduce diff with upstream
---

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index b5114758c..9a316fc96 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -20,16 +20,14 @@
 
 // Convert negative-polarity reset to positive-polarity
 (* techmap_celltype = "$_DFF_NN0_" *)
-module _90_dff_nn0_to_np0(input D, C, R, output Q); \$_DFF_NP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+module _90_dff_nn0_to_np0 (input D, C, R, output Q); \$_DFF_NP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
 (* techmap_celltype = "$_DFF_PN0_" *)
-module _90_dff_pn0_to_pp0(input D, C, R, output Q); \$_DFF_PP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-
+module _90_dff_pn0_to_pp0 (input D, C, R, output Q); \$_DFF_PP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
 (* techmap_celltype = "$_DFF_NN1_" *)
 module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
 (* techmap_celltype = "$_DFF_PN1_" *)
 module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
 
-
 module \$__SHREG_ (input C, input D, input E, output Q);
   parameter DEPTH = 0;
   parameter [DEPTH-1:0] INIT = 0;