From: lkcl Date: Sun, 3 Jan 2021 13:51:49 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~633 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=00f69c402dda8b797247cccc6afaff632500a7e5;p=libreriscv.git --- diff --git a/openpower/sv/propagation.mdwn b/openpower/sv/propagation.mdwn index a2c2ff622..b166746b3 100644 --- a/openpower/sv/propagation.mdwn +++ b/openpower/sv/propagation.mdwn @@ -26,7 +26,7 @@ There are 4 64 bit SPRs used for storing Context, and the data is stored as foll When each LSB is nonzero in any one of the seven Shift Registers the corresponding Contexts are looked up and merged (ORed) together. Contexts for different purposes however may not be mixed: an illegal instruction is raised if this occurs. -The reason for merging the contexts is so that different aspects msy be applied. For example some `RM` contexts may indicate that predication is to be applied to an instruction whilst another context may contain the svp64 Mode. Combining the two allows the predication aspect to be merged and shared, making for better packing. +The reason for merging the contexts is so that different aspects may be applied. For example some `RM` contexts may indicate that predication is to be applied to an instruction whilst another context may contain the svp64 Mode. Combining the two allows the predication aspect to be merged and shared, making for better packing. These changes occur on a precise schedule: compilers should not have difficulties statically allocating the Context Propagation, as long as certain conventions are followed, such as avoidance of allowing the context to propagate through branches used by more than one incoming path, and variable-length loops.