From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 26 Jul 2022 15:37:40 +0000 (+0100)
Subject: add first FP "expected state" use it in fmvis
X-Git-Tag: sv_maxu_works-initial~216
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=00f6e02363eef2756801ead08591eb1e0b4b2bbd;p=openpower-isa.git

add first FP "expected state" use it in fmvis
---

diff --git a/src/openpower/test/alu/fmvis_cases.py b/src/openpower/test/alu/fmvis_cases.py
index f3f75530..cca4fb49 100644
--- a/src/openpower/test/alu/fmvis_cases.py
+++ b/src/openpower/test/alu/fmvis_cases.py
@@ -23,5 +23,5 @@ class FMVISTestCase(TestAccumulatorBase):
         expected_fprs[5] = 0x4000000000000000 # 2.0 in FP64 form
         expected_fprs[6] = 0x2122000000000000
         expected_fprs[7] = 0x3FD0000000000000 # 0.25 in FP64 form
-        e = ExpectedState(pc=4) # TODO, add FPRs
-        self.add_case(Program(lst, bigendian, e))
+        e = ExpectedState(pc=4, fp_regs=expected_fprs) # TODO, add FPRs
+        self.add_case(Program(lst, bigendian), expected=e)
diff --git a/src/openpower/test/state.py b/src/openpower/test/state.py
index f8eae648..c20e75d3 100644
--- a/src/openpower/test/state.py
+++ b/src/openpower/test/state.py
@@ -73,6 +73,7 @@ class State:
     memory - stored as a dictionary {location: data}
     """
     def get_state(self):
+        yield from self.get_fpregs()
         yield from self.get_intregs()
         yield from self.get_crregs()
         yield from self.get_xregs()
@@ -80,6 +81,17 @@ class State:
         yield from self.get_mem()
 
     def compare(self, s2):
+        # Compare FP registers
+        for i, (fpreg, fpreg2) in enumerate(
+                zip(self.fpregs, s2.fpregs)):
+            log("asserting...reg", i, fpreg, fpreg2)
+            log("code, frepr(code)", self.code, repr(self.code))
+            self.dut.assertEqual(fpreg, fpreg2,
+                "fp reg %d (%s) not equal (%s) %s. "
+                " got %x  expected %x at pc %x %x\n" %
+                (i, self.state_type, s2.state_type, repr(self.code),
+                fpreg, fpreg2, self.pc, s2.pc))
+
         # Compare int registers
         for i, (intreg, intreg2) in enumerate(
                 zip(self.intregs, s2.intregs)):
@@ -175,6 +187,15 @@ class SimState(State):
     def __init__(self, sim):
         self.sim = sim
 
+    def get_fpregs(self):
+        if False:
+            yield
+        self.fpregs = []
+        for i in range(32):
+            simregval = self.sim.fpr[i].asint()
+            self.fpregs.append(simregval)
+        log("class sim fp regs", list(map(hex, self.fpregs)))
+
     def get_intregs(self):
         if False:
             yield
@@ -238,7 +259,12 @@ class ExpectedState(State):
     see openpower/test/shift_rot/shift_rot_cases2.py for examples
     """
     def __init__(self, int_regs=None, pc=0, crregs=None,
-                 so=0, ov=0, ca=0):
+                 so=0, ov=0, ca=0, fp_regs=None):
+        if fp_regs is None:
+            fp_regs = 32
+        if isinstance(fp_regs, int):
+            fp_regs = [0] * fp_regs
+        self.fpregs = deepcopy(fp_regs)
         if int_regs is None:
             int_regs = 32
         if isinstance(int_regs, int):
@@ -254,6 +280,8 @@ class ExpectedState(State):
         self.ov = ov
         self.ca = ca
 
+    def get_fpregs(self):
+        if False: yield
     def get_intregs(self):
         if False: yield
     def get_crregs(self):