From: Henry Cook Date: Thu, 1 Mar 2018 09:15:02 +0000 (-0800) Subject: periphery: bus api update (#50) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=00fbfb6dd8bd8d52588fc58ab98165ffdc132d17;p=sifive-blocks.git periphery: bus api update (#50) --- diff --git a/src/main/scala/devices/gpio/GPIOPeriphery.scala b/src/main/scala/devices/gpio/GPIOPeriphery.scala index 149f707..21fb680 100644 --- a/src/main/scala/devices/gpio/GPIOPeriphery.scala +++ b/src/main/scala/devices/gpio/GPIOPeriphery.scala @@ -3,17 +3,18 @@ package sifive.blocks.devices.gpio import Chisel._ import freechips.rocketchip.config.Field -import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus} +import freechips.rocketchip.subsystem.BaseSubsystem import freechips.rocketchip.diplomacy.{LazyModule,LazyModuleImp} import freechips.rocketchip.util.HeterogeneousBag case object PeripheryGPIOKey extends Field[Seq[GPIOParams]] -trait HasPeripheryGPIO extends HasPeripheryBus with HasInterruptBus { +trait HasPeripheryGPIO { this: BaseSubsystem => val gpioParams = p(PeripheryGPIOKey) - val gpios = gpioParams map { params => - val gpio = LazyModule(new TLGPIO(pbus.beatBytes, params)) - gpio.node := pbus.toVariableWidthSlaves + val gpios = gpioParams.zipWithIndex.map { case(params, i) => + val name = Some(s"gpio_$i") + val gpio = LazyModule(new TLGPIO(pbus.beatBytes, params)).suggestName(name) + pbus.toVariableWidthSlave(name) { gpio.node } ibus.fromSync := gpio.intnode gpio } diff --git a/src/main/scala/devices/i2c/I2CPeriphery.scala b/src/main/scala/devices/i2c/I2CPeriphery.scala index d4ad9fe..a5fbd54 100644 --- a/src/main/scala/devices/i2c/I2CPeriphery.scala +++ b/src/main/scala/devices/i2c/I2CPeriphery.scala @@ -3,16 +3,17 @@ package sifive.blocks.devices.i2c import Chisel._ import freechips.rocketchip.config.Field -import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus} +import freechips.rocketchip.subsystem.BaseSubsystem import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} case object PeripheryI2CKey extends Field[Seq[I2CParams]] -trait HasPeripheryI2C extends HasPeripheryBus { +trait HasPeripheryI2C { this: BaseSubsystem => val i2cParams = p(PeripheryI2CKey) - val i2c = i2cParams map { params => - val i2c = LazyModule(new TLI2C(pbus.beatBytes, params)) - i2c.node := pbus.toVariableWidthSlaves + val i2c = i2cParams.zipWithIndex.map { case(params, i) => + val name = Some(s"i2c_$i") + val i2c = LazyModule(new TLI2C(pbus.beatBytes, params)).suggestName(name) + pbus.toVariableWidthSlave(name) { i2c.node } ibus.fromSync := i2c.intnode i2c } diff --git a/src/main/scala/devices/mockaon/MockAONPeriphery.scala b/src/main/scala/devices/mockaon/MockAONPeriphery.scala index f7f563b..0aa4aa7 100644 --- a/src/main/scala/devices/mockaon/MockAONPeriphery.scala +++ b/src/main/scala/devices/mockaon/MockAONPeriphery.scala @@ -3,26 +3,22 @@ package sifive.blocks.devices.mockaon import Chisel._ import freechips.rocketchip.config.Field -import freechips.rocketchip.util.SynchronizerShiftReg -import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus} import freechips.rocketchip.devices.debug.HasPeripheryDebug -import freechips.rocketchip.devices.tilelink.HasPeripheryClint +import freechips.rocketchip.devices.tilelink.HasPeripheryCLINT import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} -import freechips.rocketchip.tilelink.{TLAsyncCrossingSource} import freechips.rocketchip.interrupts._ -import freechips.rocketchip.util.ResetCatchAndSync +import freechips.rocketchip.subsystem.BaseSubsystem +import freechips.rocketchip.tilelink.{TLAsyncCrossingSource} +import freechips.rocketchip.util.{ResetCatchAndSync, SynchronizerShiftReg} case object PeripheryMockAONKey extends Field[MockAONParams] -trait HasPeripheryMockAON extends HasPeripheryBus - with HasInterruptBus - with HasPeripheryClint - with HasPeripheryDebug { +trait HasPeripheryMockAON extends HasPeripheryCLINT with HasPeripheryDebug { this: BaseSubsystem => // We override the clock & Reset here so that all synchronizers, etc // are in the proper clock domain. val mockAONParams= p(PeripheryMockAONKey) val aon = LazyModule(new MockAONWrapper(pbus.beatBytes, mockAONParams)) - aon.node := TLAsyncCrossingSource() := pbus.toVariableWidthSlaves + pbus.toVariableWidthSlave(Some("aon")) { aon.node := TLAsyncCrossingSource() } ibus.fromSync := IntSyncCrossingSink() := aon.intnode } diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala index 00043ab..e098258 100644 --- a/src/main/scala/devices/pwm/PWMPeriphery.scala +++ b/src/main/scala/devices/pwm/PWMPeriphery.scala @@ -3,7 +3,7 @@ package sifive.blocks.devices.pwm import Chisel._ import freechips.rocketchip.config.Field -import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus} +import freechips.rocketchip.subsystem.BaseSubsystem import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} import freechips.rocketchip.util.HeterogeneousBag import sifive.blocks.devices.pinctrl.{Pin} @@ -16,11 +16,12 @@ class PWMPortIO(val c: PWMParams) extends Bundle { case object PeripheryPWMKey extends Field[Seq[PWMParams]] -trait HasPeripheryPWM extends HasPeripheryBus with HasInterruptBus { +trait HasPeripheryPWM { this: BaseSubsystem => val pwmParams = p(PeripheryPWMKey) - val pwms = pwmParams map { params => - val pwm = LazyModule(new TLPWM(pbus.beatBytes, params)) - pwm.node := pbus.toVariableWidthSlaves + val pwms = pwmParams.zipWithIndex.map { case(params, i) => + val name = Some(s"pwm_$i") + val pwm = LazyModule(new TLPWM(pbus.beatBytes, params)).suggestName(name) + pbus.toVariableWidthSlave(name) { pwm.node } ibus.fromSync := pwm.intnode pwm } diff --git a/src/main/scala/devices/pwm/PWMPins.scala b/src/main/scala/devices/pwm/PWMPins.scala index 03acc90..aa7e032 100644 --- a/src/main/scala/devices/pwm/PWMPins.scala +++ b/src/main/scala/devices/pwm/PWMPins.scala @@ -2,10 +2,6 @@ package sifive.blocks.devices.pwm import Chisel._ -import freechips.rocketchip.config.Field -import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus} -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} -import freechips.rocketchip.util.HeterogeneousBag import sifive.blocks.devices.pinctrl.{Pin} class PWMSignals[T <: Data] (pingen: ()=> T, val c: PWMParams) extends Bundle { diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala index dd76d15..37fe3d9 100644 --- a/src/main/scala/devices/spi/SPIPeriphery.scala +++ b/src/main/scala/devices/spi/SPIPeriphery.scala @@ -3,18 +3,19 @@ package sifive.blocks.devices.spi import Chisel._ import freechips.rocketchip.config.Field -import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus} +import freechips.rocketchip.subsystem.BaseSubsystem import freechips.rocketchip.diplomacy.{LazyModule,LazyModuleImp,BufferParams} import freechips.rocketchip.tilelink.{TLFragmenter,TLBuffer} import freechips.rocketchip.util.HeterogeneousBag case object PeripherySPIKey extends Field[Seq[SPIParams]] -trait HasPeripherySPI extends HasPeripheryBus with HasInterruptBus { +trait HasPeripherySPI { this: BaseSubsystem => val spiParams = p(PeripherySPIKey) - val spis = spiParams map { params => - val spi = LazyModule(new TLSPI(pbus.beatBytes, params)) - spi.rnode := pbus.toVariableWidthSlaves + val spis = spiParams.zipWithIndex.map { case(params, i) => + val name = Some(s"spi_$i") + val spi = LazyModule(new TLSPI(pbus.beatBytes, params)).suggestName(name) + pbus.toVariableWidthSlave(name) { spi.rnode } ibus.fromSync := spi.intnode spi } @@ -36,15 +37,16 @@ trait HasPeripherySPIModuleImp extends LazyModuleImp with HasPeripherySPIBundle case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]] -trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus { +trait HasPeripherySPIFlash { this: BaseSubsystem => val spiFlashParams = p(PeripherySPIFlashKey) - val qspis = spiFlashParams map { params => + val qspis = spiFlashParams.zipWithIndex.map { case(params, i) => + val name = Some(s"qspi_$i") val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params)) - qspi.rnode := pbus.toVariableWidthSlaves - (qspi.fnode - := TLFragmenter(1, pbus.blockBytes) - := TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none) - := pbus.toFixedWidthSlaves) + pbus.toVariableWidthSlave(name) { qspi.rnode } + qspi.fnode := pbus.toFixedWidthSlave(name) { + TLFragmenter(1, pbus.blockBytes) := + TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none) + } ibus.fromSync := qspi.intnode qspi } diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala index d1db77b..6ccc9e7 100644 --- a/src/main/scala/devices/uart/UARTPeriphery.scala +++ b/src/main/scala/devices/uart/UARTPeriphery.scala @@ -4,17 +4,18 @@ package sifive.blocks.devices.uart import Chisel._ import chisel3.experimental.{withClockAndReset} import freechips.rocketchip.config.Field -import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} +import freechips.rocketchip.subsystem.{BaseSubsystem, PeripheryBusKey} case object PeripheryUARTKey extends Field[Seq[UARTParams]] -trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus { +trait HasPeripheryUART { this: BaseSubsystem => private val divinit = (p(PeripheryBusKey).frequency / 115200).toInt val uartParams = p(PeripheryUARTKey).map(_.copy(divisorInit = divinit)) - val uarts = uartParams map { params => - val uart = LazyModule(new TLUART(pbus.beatBytes, params)) - uart.node := pbus.toVariableWidthSlaves + val uarts = uartParams.zipWithIndex.map { case(params, i) => + val name = Some(s"uart_$i") + val uart = LazyModule(new TLUART(pbus.beatBytes, params)).suggestName(name) + pbus.toVariableWidthSlave(name) { uart.node } ibus.fromSync := uart.intnode uart } diff --git a/src/main/scala/devices/uart/UARTPins.scala b/src/main/scala/devices/uart/UARTPins.scala index 4201f90..aeb3632 100644 --- a/src/main/scala/devices/uart/UARTPins.scala +++ b/src/main/scala/devices/uart/UARTPins.scala @@ -3,10 +3,7 @@ package sifive.blocks.devices.uart import Chisel._ import chisel3.experimental.{withClockAndReset} -import freechips.rocketchip.config.Field import freechips.rocketchip.util.SyncResetSynchronizerShiftReg -import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus} -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} import sifive.blocks.devices.pinctrl.{Pin} class UARTSignals[T <: Data] (pingen: () => T) extends Bundle {