From: whitequark <whitequark@whitequark.org>
Date: Mon, 24 Dec 2018 19:11:07 +0000 (+0000)
Subject: back.rtlil: unbreak d47c1f8a.
X-Git-Tag: working~127
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=010ddb96b5c0e75219ed819625d705b0337ed485;p=nmigen.git

back.rtlil: unbreak d47c1f8a.
---

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index bc98975..c51b4b9 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -644,7 +644,7 @@ def convert_fragment(builder, fragment, name, top):
                             memories[memory] = module.memory(width=memory.width, size=memory.depth,
                                                              name=memory.name)
                             addr_bits = bits_for(memory.depth)
-                            data_parts = ["{}'".format(memory.width * memory.depth)]
+                            data_parts = []
                             for addr in range(memory.depth):
                                 if addr < len(memory.init):
                                     data = memory.init[addr]
@@ -653,7 +653,8 @@ def convert_fragment(builder, fragment, name, top):
                                 data_parts.append("{:0{}b}".format(data, memory.width))
                             module.cell("$meminit", ports={
                                 "\\ADDR": rhs_compiler(ast.Const(0, addr_bits)),
-                                "\\DATA": "".join(data_parts),
+                                "\\DATA": "{}'".format(memory.width * memory.depth) +
+                                          "".join(reversed(data_parts)),
                             }, params={
                                 "MEMID": memories[memory],
                                 "ABITS": addr_bits,