From: lkcl <lkcl@web>
Date: Thu, 20 Oct 2022 22:02:39 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~65
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=01101624b31823fcaf9772f905085c3d0b9922fb;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn
index 261013339..3ae673fe7 100644
--- a/openpower/sv/rfc/ls003.mdwn
+++ b/openpower/sv/rfc/ls003.mdwn
@@ -76,6 +76,9 @@ allowing highly-efficient arbitrary-length big-integer division.
    VSX is 128/128.
 5. `maddedu` and `divmod2du` are full inverses of each other, including
   when used for arbitrary-length big-integer arithmetic
+6. These are both 3-in 2-out instructions. If Power ISA did not already
+  have LD/ST-with-update instructions and instructions with `RAp`
+  and `RTp` then these instructions would not be proposed.
 
 **Changes**