From: Jan Hubicka <hubicka@ucw.cz>
Date: Mon, 16 Oct 2017 17:39:01 +0000 (+0200)
Subject: * x86-tune-costs.h (znver1_cost): Fix move cost tables.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=01118373fe07a1329bb33d00c286f59c6e7f15b1;p=gcc.git

* x86-tune-costs.h (znver1_cost): Fix move cost tables.

From-SVN: r253790
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 572520e811e..ab0d1f6ac63 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2017-10-16  Jan Hubicka  <hubicka@ucw.cz>
+
+	* x86-tune-costs.h (znver1_cost): Fix move cost tables.
+
 2017-10-16  Olivier Hainque  <hainque@adacore.com>
 
 	* gcc/config.gcc (powerpc*-*-*spe*): Pick 8548 as the default
diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h
index c5ded939237..6a482ddea5b 100644
--- a/gcc/config/i386/x86-tune-costs.h
+++ b/gcc/config/i386/x86-tune-costs.h
@@ -1455,29 +1455,34 @@ struct processor_costs znver1_cost = {
   COSTS_N_INSNS (1),			/* cost of movzx.  */
   8,					/* "large" insn.  */
   9,					/* MOVE_RATIO.  */
-  4,					/* cost for loading QImode using
+
+  /* reg-reg moves are done by renaming and thus they are even cheaper than
+     1 cycle. Becuase reg-reg move cost is 2 and the following tables correspond
+     to doubles of latencies, we do not model this correctly.  It does not
+     seem to make practical difference to bump prices up even more.  */
+  6,					/* cost for loading QImode using
 					   movzbl.  */
-  {5, 5, 4},				/* cost of loading integer registers
+  {6, 6, 6},				/* cost of loading integer registers
 					   in QImode, HImode and SImode.
 					   Relative to reg-reg move (2).  */
-  {4, 4, 4},				/* cost of storing integer
+  {8, 8, 8},				/* cost of storing integer
 					   registers.  */
   2,					/* cost of reg,reg fld/fst.  */
-  {5, 5, 12},				/* cost of loading fp registers
+  {6, 6, 16},				/* cost of loading fp registers
 		   			   in SFmode, DFmode and XFmode.  */
-  {4, 4, 8},				/* cost of storing fp registers
+  {8, 8, 16},				/* cost of storing fp registers
  		   			   in SFmode, DFmode and XFmode.  */
   2,					/* cost of moving MMX register.  */
-  {4, 4},				/* cost of loading MMX registers
+  {6, 6},				/* cost of loading MMX registers
 					   in SImode and DImode.  */
-  {4, 4},				/* cost of storing MMX registers
+  {8, 8},				/* cost of storing MMX registers
 					   in SImode and DImode.  */
   2,					/* cost of moving SSE register.  */
-  {4, 4, 4},				/* cost of loading SSE registers
+  {6, 6, 6},				/* cost of loading SSE registers
 					   in SImode, DImode and TImode.  */
-  {4, 4, 4},				/* cost of storing SSE registers
+  {8, 8, 8},				/* cost of storing SSE registers
 					   in SImode, DImode and TImode.  */
-  2,					/* MMX or SSE register to integer.  */
+  6,					/* MMX or SSE register to integer.  */
   32,					/* size of l1 cache.  */
   512,					/* size of l2 cache.  */
   64,					/* size of prefetch block.  */