From: Luke Kenneth Casson Leighton Date: Mon, 29 Jun 2020 15:08:16 +0000 (+0100) Subject: use correct ALUHelpers in div test X-Git-Tag: div_pipeline~197 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=01163c3bd63e6a48f0eef65d3a98ed74e11d499c;p=soc.git use correct ALUHelpers in div test --- diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py index e26e04fa..25dedf8b 100644 --- a/src/soc/fu/div/test/test_pipe_caller.py +++ b/src/soc/fu/div/test/test_pipe_caller.py @@ -25,7 +25,7 @@ def get_cu_inputs(dec2, sim): yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB - yield from ALUHelpers.get_sim_xer_ca(res, sim, dec2) # XER.ca + yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2) # XER.ca yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so print ("alu get_cu_inputs", res) @@ -197,7 +197,7 @@ class TestRunner(FHDLTestCase): yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2) yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2) yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2) - yield from ALUHelpers.get_sim_xer_ca(sim_o, sim, dec2) + yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2) yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2) ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))