From: lkcl <lkcl@web>
Date: Sat, 13 May 2023 12:34:33 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=01319133f6d99653fa469661e4b68d8f752f639e;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 828e32905..509034282 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -77,8 +77,8 @@ SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:
 
 |6 | 7 |19:20|21 | 22:23   |  description     |
 |--|---|-----|---|---------|------------------|
-|/ | / |RG 0 | 0 | dz  sz  | simple mode                      |
-|/ | / |RG 0 | 1 | dz  sz  | scalar reduce mode (mapreduce) |
+|/ | / |0  0 |RG | dz  sz  | simple mode                      |
+|/ | / |1  0 |RG | dz  sz  | scalar reduce mode (mapreduce) |
 |zz|SNZ|VLI 1|inv|  CR-bit | Ffirst 3-bit mode      |
 |/ |SNZ|VLI 1|inv|  dz sz  | Ffirst 5-bit mode (implies CR-bit from result) |