From: lkcl <lkcl@web>
Date: Sat, 23 Jul 2022 11:02:39 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1092
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=013a78cd76f080d11da438285e4cb50228b7f6a0;p=libreriscv.git

---

diff --git a/openpower/sv/executive_summary.mdwn b/openpower/sv/executive_summary.mdwn
index 21f9732af..09788b519 100644
--- a/openpower/sv/executive_summary.mdwn
+++ b/openpower/sv/executive_summary.mdwn
@@ -11,6 +11,16 @@ It is extremely important to think of Simple-V as a 2-Dimensional ISA:
 instructions vertical and registers horizontal otherwise it will be
 difficult to grasp and appreciate its RISC simplicity.
 
+Like all Cray-Style Scalable Vector ISAs, Simple-V binaries remain
+ubiquitous: the ISA uniform.  GPUs may implement massive-wide
+SIMD back-ends, focussing on
+number-crunching.  Existing Multi-issue Superscalar implementations may
+insert Simple-V between decode and issue with minimal disruption.
+Single-issue in-order implementations are very straightforward.  All
+implementations regardless of back-end capability may execute the exact
+same binaries *(this is known to be extremely important to the Power ISA
+ecosystem)*.
+
 Simple-V is **not RISC-V and is not RISC-V Vectors**. NEC SX Aurora,
 RVV and Simple-V are all based on Cray-style Vectors hence the similarity,
 the provision of a `setvl` instruction and why they are each called