From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 14 Sep 2014 12:49:53 +0000 (+0200)
Subject: Various fixes/cleanups in alumacc and maccmap
X-Git-Tag: yosys-0.4~132
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=014bb34e0ecd058545fafbf1dbb0ba5064714c1d;p=yosys.git

Various fixes/cleanups in alumacc and maccmap
---

diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index d6ee9e66c..3fddcef13 100644
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -443,7 +443,6 @@ struct AlumaccWorker
 			n->alu_cell->setPort("\\X", module->addWire(NEW_ID, SIZE(n->y)));
 			n->alu_cell->setPort("\\CO", module->addWire(NEW_ID, SIZE(n->y)));
 			n->alu_cell->fixup_parameters(n->is_signed, n->is_signed);
-			log_cell(n->alu_cell);
 
 			for (auto &it : n->cmp)
 			{
diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc
index c2dc9aa8a..e17231cb5 100644
--- a/passes/techmap/maccmap.cc
+++ b/passes/techmap/maccmap.cc
@@ -208,7 +208,17 @@ struct MaccmapWorker
 
 		log_assert(tree_sum_bits.empty());
 
-		return module->Add(NEW_ID, summands.front(), summands.back());
+		RTLIL::Cell *c = module->addCell(NEW_ID, "$alu");
+		c->setPort("\\A", summands.front());
+		c->setPort("\\B", summands.back());
+		c->setPort("\\CI", RTLIL::S0);
+		c->setPort("\\BI", RTLIL::S0);
+		c->setPort("\\Y", module->addWire(NEW_ID, width));
+		c->setPort("\\X", module->addWire(NEW_ID, width));
+		c->setPort("\\CO", module->addWire(NEW_ID, width));
+		c->fixup_parameters();
+
+		return c->getPort("\\Y");
 	}
 };