From: Gabriel Somlo Date: Thu, 31 Oct 2019 20:23:36 +0000 (-0400) Subject: soc_sdram: remove upper limit on usable main RAM X-Git-Tag: 24jan2021_ls180~881^2~1 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=014db664440525abcf6442ce2493ddcf257025dd;p=litex.git soc_sdram: remove upper limit on usable main RAM Revert commit #68a503174. --- diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py index f16e596a..71f54b17 100644 --- a/litex/soc/integration/soc_sdram.py +++ b/litex/soc/integration/soc_sdram.py @@ -61,7 +61,6 @@ class SoCSDRAM(SoCCore): main_ram_size = 2**(geom_settings.bankbits + geom_settings.rowbits + geom_settings.colbits)*phy.settings.databits//8 - main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now # SoC [<--> L2 Cache] <--> LiteDRAM ---------------------------------------------------- if self.cpu.name == "rocket":