From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 25 Sep 2019 12:09:44 +0000 (+0200)
Subject: targets/ulx3s: revert to cl=2
X-Git-Tag: 24jan2021_ls180~984
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=015b65fe88b5b59899869e7ca30126986c478ed3;p=litex.git

targets/ulx3s: revert to cl=2
---

diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py
index 4a80ee6f..f1e21ba7 100755
--- a/litex/boards/targets/ulx3s.py
+++ b/litex/boards/targets/ulx3s.py
@@ -63,7 +63,7 @@ class BaseSoC(SoCSDRAM):
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
         if not self.integrated_main_ram_size:
-            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=3)
+            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2)
             sdram_module = MT48LC16M16(sys_clk_freq, "1:1")
             self.register_sdram(self.sdrphy,
                                 sdram_module.geom_settings,