From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 17 Sep 2022 20:47:02 +0000 (+0100)
Subject: whoops. mode-bits need to be put in MSB0 order. sigh
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=01600a57590f173ff216e1ae6d140ae07fb5ebda;p=openpower-isa.git

whoops. mode-bits need to be put in MSB0 order. sigh
---

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index c617375a..b6944855 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1349,8 +1349,11 @@ class SVP64Asm:
                     mode |= (predresult << SVP64MODE.BO_LSB)  # set BO
 
         # whewww.... modes all done :)
-        # now put into svp64_rm
-        mode |= sv_mode
+        # now put into svp64_rm, but respect MSB0 order
+        if sv_mode&1:
+            mode |= (0b1<<SVP64MODE.MOD2_LSB)
+        if sv_mode&2:
+            mode |= (0b1<<SVP64MODE.MOD2_MSB)
         # mode: bits 19-23
         svp64_rm.mode = mode