From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 5 Sep 2019 17:07:56 +0000 (-0700)
Subject: Cleanup
X-Git-Tag: working-ls180~1039^2~200
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0166e02e781080f346b37dcb3ba6f9fa947ca22d;p=yosys.git

Cleanup
---

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 339ac646c..ed5bd3aae 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -1,14 +1,14 @@
 pattern xilinx_dsp
 
 state <SigBit> clock
-state <SigSpec> sigA sigffAmux sigB sigC sigM sigP sigPused
+state <SigSpec> sigA sigffAmux sigB sigC sigM sigP
 state <IdString> ffAmuxAB ffMmuxAB postAddAB postAddMuxAB
 
 match dsp
 	select dsp->type.in(\DSP48E1)
 endmatch
 
-code sigA sigB
+code sigA sigffAmux sigB sigM
 	sigA = port(dsp, \A);
 	int i;
 	for (i = GetSize(sigA)-1; i > 0; i--)
@@ -26,12 +26,9 @@ code sigA sigB
 	if (sigB[i].wire)
 		++i;
 	sigB.remove(i, GetSize(sigB)-i);
-endcode
 
-code sigM
 	SigSpec P = port(dsp, \P);
 	// Only care about those bits that are used
-	int i;
 	for (i = 0; i < GetSize(P); i++) {
 		if (nusers(P[i]) <= 1)
 			break;