From: H.J. Lu <hongjiu.lu@intel.com>
Date: Wed, 15 May 2019 15:20:28 +0000 (+0000)
Subject: i386: Emulate MMX mmx_psadbw with SSE
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=018a45bdf3e3cbed5fbdd6db19457c63fea5f7bf;p=gcc.git

i386: Emulate MMX mmx_psadbw with SSE

Emulate MMX mmx_psadbw with SSE.  Only SSE register source operand is
allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_psadbw): Add SSE emulation.

From-SVN: r271237
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index eefdecdb602..84cf0aabff1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2019-05-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/89021
+	* config/i386/mmx.md (mmx_psadbw): Add SSE emulation.
+
 2019-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR target/89021
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 338f77e59f8..15fd355eeb2 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1796,14 +1796,19 @@
    (set_attr "mode" "DI,TI,TI")])
 
 (define_insn "mmx_psadbw"
-  [(set (match_operand:V1DI 0 "register_operand" "=y")
-        (unspec:V1DI [(match_operand:V8QI 1 "register_operand" "0")
-		      (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
+  [(set (match_operand:V1DI 0 "register_operand" "=y,x,Yv")
+        (unspec:V1DI [(match_operand:V8QI 1 "register_operand" "0,0,Yv")
+		      (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yv")]
 		     UNSPEC_PSADBW))]
-  "TARGET_SSE || TARGET_3DNOW_A"
-  "psadbw\t{%2, %0|%0, %2}"
-  [(set_attr "type" "mmxshft")
-   (set_attr "mode" "DI")])
+  "(TARGET_MMX || TARGET_MMX_WITH_SSE)
+   && (TARGET_SSE || TARGET_3DNOW_A)"
+  "@
+   psadbw\t{%2, %0|%0, %2}
+   psadbw\t{%2, %0|%0, %2}
+   vpsadbw\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+   (set_attr "type" "mmxshft,sseiadd,sseiadd")
+   (set_attr "mode" "DI,TI,TI")])
 
 (define_insn_and_split "mmx_pmovmskb"
   [(set (match_operand:SI 0 "register_operand" "=r,r")