From: Michael Nolan <mtnolan2640@gmail.com>
Date: Fri, 15 May 2020 22:55:55 +0000 (-0400)
Subject: Fix bug introduced when I made it possible to set the initial state of CR
X-Git-Tag: div_pipeline~1155
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=01a1c19531e272d020a1716d97cc555e3b4fae6f;p=soc.git

Fix bug introduced when I made it possible to set the initial state of CR
---

diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py
index f9497c7c..d56019b2 100644
--- a/src/soc/alu/test/test_pipe_caller.py
+++ b/src/soc/alu/test/test_pipe_caller.py
@@ -200,7 +200,7 @@ class TestRunner(FHDLTestCase):
                 print(test.name)
                 program = test.program
                 self.subTest(test.name)
-                simulator = ISA(pdecode2, test.regs, test.sprs)
+                simulator = ISA(pdecode2, test.regs, test.sprs, 0)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
 
diff --git a/src/soc/logical/test/test_pipe_caller.py b/src/soc/logical/test/test_pipe_caller.py
index 82b62b06..190a9ade 100644
--- a/src/soc/logical/test/test_pipe_caller.py
+++ b/src/soc/logical/test/test_pipe_caller.py
@@ -202,7 +202,7 @@ class TestRunner(FHDLTestCase):
                 print(test.name)
                 program = test.program
                 self.subTest(test.name)
-                simulator = ISA(pdecode2, test.regs, test.sprs)
+                simulator = ISA(pdecode2, test.regs, test.sprs, 0)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
 
diff --git a/src/soc/shift_rot/test/test_pipe_caller.py b/src/soc/shift_rot/test/test_pipe_caller.py
index 97df2f20..3244332b 100644
--- a/src/soc/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/shift_rot/test/test_pipe_caller.py
@@ -219,7 +219,7 @@ class TestRunner(FHDLTestCase):
                 print(test.name)
                 program = test.program
                 self.subTest(test.name)
-                simulator = ISA(pdecode2, test.regs, test.sprs)
+                simulator = ISA(pdecode2, test.regs, test.sprs, 0)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))