From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Thu, 7 Apr 2016 06:42:22 +0000 (-0700)
Subject: Fixed assertion failure for non-inferrable counters in some cases
X-Git-Tag: yosys-0.7~263^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=01a5f711871658c9997f7352414cd4ac50ed772c;p=yosys.git

Fixed assertion failure for non-inferrable counters in some cases
---

diff --git a/techlibs/greenpak4/greenpak4_counters.cc b/techlibs/greenpak4/greenpak4_counters.cc
index 394f3dab1..7b5646bf2 100644
--- a/techlibs/greenpak4/greenpak4_counters.cc
+++ b/techlibs/greenpak4/greenpak4_counters.cc
@@ -248,8 +248,12 @@ void greenpak4_counters_worker(
 	if (cell->type != "$alu")
 		return;
 	
-	//A input is the count value. Check if it has COUNT_EXTRACT set
-	RTLIL::Wire* a_wire = sigmap(cell->getPort("\\A")).as_wire();
+	//A input is the count value. Check if it has COUNT_EXTRACT set.
+	//If it's not a wire, don't even try
+	auto port = sigmap(cell->getPort("\\A"));
+	if(!port.is_wire())
+		return;
+	RTLIL::Wire* a_wire = port.as_wire();
 	bool force_extract = false;
 	bool never_extract = false;
 	string count_reg_src = a_wire->attributes["\\src"].decode_string().c_str();