From: Segher Boessenkool Date: Tue, 29 Nov 2016 05:51:51 +0000 (+0100) Subject: rs6000: Testcases for rl*i* X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=01a8a373399f292d15f3ac882add6c585315a0cb;p=gcc.git rs6000: Testcases for rl*i* These testcases test that we generate the expected code for all of the rl*i* instructions, that is, rotate-and-mask and rotate-and-mask-insert for immediate rotation counts. All the testcases do rotate, shift left, as well as shift right; if that results in an instruction that does not exist the testcases generate a multiplication instead, so that we can detect if this is handled properly. Many 32-bit instructions zero-extend their result properly in 64-bit mode, but the rs6000 port does not yet know. These testcases test the status quo, so they will need updating when ever we handle this. gcc/testsuite/ * gcc.target/powerpc/rldic-0.c: New testcase. * gcc.target/powerpc/rldic-1.c: New testcase. * gcc.target/powerpc/rldic-2.c: New testcase. * gcc.target/powerpc/rldicl-0.c: New testcase. * gcc.target/powerpc/rldicl-1.c: New testcase. * gcc.target/powerpc/rldicl-2.c: New testcase. * gcc.target/powerpc/rldicr-0.c: New testcase. * gcc.target/powerpc/rldicr-1.c: New testcase. * gcc.target/powerpc/rldicr-2.c: New testcase. * gcc.target/powerpc/rldicx.h: New file. * gcc.target/powerpc/rldimi-0.c: New testcase. * gcc.target/powerpc/rldimi-1.c: New testcase. * gcc.target/powerpc/rldimi-2.c: New testcase. * gcc.target/powerpc/rldimi.h: New file. * gcc.target/powerpc/rlwimi-0.c: New testcase. * gcc.target/powerpc/rlwimi-1.c: New testcase. * gcc.target/powerpc/rlwimi-2.c: New testcase. * gcc.target/powerpc/rlwimi.h: New file. * gcc.target/powerpc/rlwinm-0.c: New testcase. * gcc.target/powerpc/rlwinm-1.c: New testcase. * gcc.target/powerpc/rlwinm-2.c: New testcase. * gcc.target/powerpc/rlwinm.h: New file. From-SVN: r242951 --- diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a63953ca891..b325e2c9d58 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,28 @@ +2016-11-29 Segher Boessenkool + + * gcc.target/powerpc/rldic-0.c: New testcase. + * gcc.target/powerpc/rldic-1.c: New testcase. + * gcc.target/powerpc/rldic-2.c: New testcase. + * gcc.target/powerpc/rldicl-0.c: New testcase. + * gcc.target/powerpc/rldicl-1.c: New testcase. + * gcc.target/powerpc/rldicl-2.c: New testcase. + * gcc.target/powerpc/rldicr-0.c: New testcase. + * gcc.target/powerpc/rldicr-1.c: New testcase. + * gcc.target/powerpc/rldicr-2.c: New testcase. + * gcc.target/powerpc/rldicx.h: New file. + * gcc.target/powerpc/rldimi-0.c: New testcase. + * gcc.target/powerpc/rldimi-1.c: New testcase. + * gcc.target/powerpc/rldimi-2.c: New testcase. + * gcc.target/powerpc/rldimi.h: New file. + * gcc.target/powerpc/rlwimi-0.c: New testcase. + * gcc.target/powerpc/rlwimi-1.c: New testcase. + * gcc.target/powerpc/rlwimi-2.c: New testcase. + * gcc.target/powerpc/rlwimi.h: New file. + * gcc.target/powerpc/rlwinm-0.c: New testcase. + * gcc.target/powerpc/rlwinm-1.c: New testcase. + * gcc.target/powerpc/rlwinm-2.c: New testcase. + * gcc.target/powerpc/rlwinm.h: New file. + 2016-11-28 Jakub Jelinek PR middle-end/78540 diff --git a/gcc/testsuite/gcc.target/powerpc/rldic-0.c b/gcc/testsuite/gcc.target/powerpc/rldic-0.c new file mode 100644 index 00000000000..ba789f6c674 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rldic-0.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 1799 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+blr} 900 } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+rldic} 870 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rotldi} 27 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 2 } } */ + + +#define CC +#define SL +#define SR + +#include "rldicx.h" diff --git a/gcc/testsuite/gcc.target/powerpc/rldic-1.c b/gcc/testsuite/gcc.target/powerpc/rldic-1.c new file mode 100644 index 00000000000..cf93a5aa6ae --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rldic-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 1799 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+blr} 900 } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+rldic} 415 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+sldi} 29 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 2 } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+mulli} 453 } } */ + + +#define CC +#define SL + +#include "rldicx.h" diff --git a/gcc/testsuite/gcc.target/powerpc/rldic-2.c b/gcc/testsuite/gcc.target/powerpc/rldic-2.c new file mode 100644 index 00000000000..ea77f767726 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rldic-2.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 1799 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+blr} 900 } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+rldic} 27 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 2 } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+mulli} 870 } } */ + + +#define CC +#define SR + +#include "rldicx.h" diff --git a/gcc/testsuite/gcc.target/powerpc/rldicl-0.c b/gcc/testsuite/gcc.target/powerpc/rldicl-0.c new file mode 100644 index 00000000000..087d427672d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rldicl-0.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 1799 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+blr} 900 } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+rldic} 841 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rotldi} 29 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+srdi} 27 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 2 } } */ + + +#define CL +#define SL +#define SR + +#include "rldicx.h" diff --git a/gcc/testsuite/gcc.target/powerpc/rldicl-1.c b/gcc/testsuite/gcc.target/powerpc/rldicl-1.c new file mode 100644 index 00000000000..3ed0b8061e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rldicl-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 1799 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+blr} 900 } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+rldic} 27 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 2 } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+mulli} 870 } } */ + + +#define CL +#define SL + +#include "rldicx.h" diff --git a/gcc/testsuite/gcc.target/powerpc/rldicl-2.c b/gcc/testsuite/gcc.target/powerpc/rldicl-2.c new file mode 100644 index 00000000000..a1f7dfcce4e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rldicl-2.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 1799 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+blr} 900 } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+rldic} 453 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+srdi} 27 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 2 } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+mulli} 417 } } */ + + +#define CL +#define SR + +#include "rldicx.h" diff --git a/gcc/testsuite/gcc.target/powerpc/rldicr-0.c b/gcc/testsuite/gcc.target/powerpc/rldicr-0.c new file mode 100644 index 00000000000..180e71259af --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rldicr-0.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 1799 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+blr} 900 } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+rldic} 870 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rotldi} 29 } } */ + + +#define CR +#define SL +#define SR + +#include "rldicx.h" diff --git a/gcc/testsuite/gcc.target/powerpc/rldicr-1.c b/gcc/testsuite/gcc.target/powerpc/rldicr-1.c new file mode 100644 index 00000000000..803ba31dea2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rldicr-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 1799 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+blr} 900 } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+rldic} 423 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+sldi} 23 } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+mulli} 453 } } */ + + +#define CR +#define SL + +#include "rldicx.h" diff --git a/gcc/testsuite/gcc.target/powerpc/rldicr-2.c b/gcc/testsuite/gcc.target/powerpc/rldicr-2.c new file mode 100644 index 00000000000..01f2fb6bbad --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rldicr-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 1799 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+blr} 900 } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+rldic} 29 } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+mulli} 870 } } */ + + +#define CR +#define SR + +#include "rldicx.h" diff --git a/gcc/testsuite/gcc.target/powerpc/rldicx.h b/gcc/testsuite/gcc.target/powerpc/rldicx.h new file mode 100644 index 00000000000..8413ea5ead4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rldicx.h @@ -0,0 +1,117 @@ +typedef unsigned int u32; +typedef unsigned long long u64; + +static inline u64 rot(u64 x, u32 n, u32 mb, u32 me) +{ + u64 y = x; + + if (n) + x = 0 +#ifdef SL + | (x << n) +#endif +#ifdef SR + | (x >> (64 - n)) +#endif + ; + + u64 s = -1; + if (n) + s = 0 +#ifdef SL + | (s << n) +#endif +#ifdef SR + | (s >> (64 - n)) +#endif + ; + + u64 mask = 0; + mask += 1ULL << (63 - mb); + mask += 1ULL << (63 - mb); + mask -= 1ULL << (63 - me); + mask -= (mb > me); + + if (mask & ~s) + return 12345*y; + + return x & mask; +} + +#ifdef CC +#define X2(N,B) \ +u64 f_##N##_##B(u64 x) { return rot(x,N,B,63-N); } +#endif +#ifdef CL +#define X2(N,B) \ +u64 f_##N##_##B(u64 x) { return rot(x,N,B,63); } +#endif +#ifdef CR +#define X2(N,E) \ +u64 f_##N##_##E(u64 x) { return rot(x,N,0,E); } +#endif + +#define X1(N) \ +X2(N,0) \ +X2(N,1) \ +X2(N,2) \ +X2(N,7) \ +X2(N,8) \ +X2(N,9) \ +X2(N,15) \ +X2(N,16) \ +X2(N,17) \ +X2(N,23) \ +X2(N,24) \ +X2(N,25) \ +X2(N,29) \ +X2(N,30) \ +X2(N,31) \ +X2(N,32) \ +X2(N,33) \ +X2(N,34) \ +X2(N,39) \ +X2(N,40) \ +X2(N,41) \ +X2(N,47) \ +X2(N,48) \ +X2(N,49) \ +X2(N,55) \ +X2(N,56) \ +X2(N,57) \ +X2(N,61) \ +X2(N,62) \ +X2(N,63) +#define X() \ +X1(0) \ +X1(1) \ +X1(2) \ +X1(7) \ +X1(8) \ +X1(9) \ +X1(15) \ +X1(16) \ +X1(17) \ +X1(23) \ +X1(24) \ +X1(25) \ +X1(29) \ +X1(30) \ +X1(31) \ +X1(32) \ +X1(33) \ +X1(34) \ +X1(39) \ +X1(40) \ +X1(41) \ +X1(47) \ +X1(48) \ +X1(49) \ +X1(55) \ +X1(56) \ +X1(57) \ +X1(61) \ +X1(62) \ +X1(63) + +X() diff --git a/gcc/testsuite/gcc.target/powerpc/rldimi-0.c b/gcc/testsuite/gcc.target/powerpc/rldimi-0.c new file mode 100644 index 00000000000..80a67ecd20c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rldimi-0.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 4471 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+blr} 1800 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+mr} 873 } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+rldimi} 1744 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rotldi} 54 } } */ + + +#define SL +#define SR + +#include "rldimi.h" diff --git a/gcc/testsuite/gcc.target/powerpc/rldimi-1.c b/gcc/testsuite/gcc.target/powerpc/rldimi-1.c new file mode 100644 index 00000000000..b6fece7aec8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rldimi-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 4045 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+blr} 1800 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+mr} 447 } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+rldimi} 892 } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+mulli} 906 } } */ + + +#define SL + +#include "rldimi.h" diff --git a/gcc/testsuite/gcc.target/powerpc/rldimi-2.c b/gcc/testsuite/gcc.target/powerpc/rldimi-2.c new file mode 100644 index 00000000000..acea28d5632 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rldimi-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 3628 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+blr} 1800 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+mr} 30 } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+rldimi} 58 } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+mulli} 1740 } } */ + + +#define SR + +#include "rldimi.h" diff --git a/gcc/testsuite/gcc.target/powerpc/rldimi.h b/gcc/testsuite/gcc.target/powerpc/rldimi.h new file mode 100644 index 00000000000..169428423c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rldimi.h @@ -0,0 +1,106 @@ +typedef unsigned int u32; +typedef unsigned long long u64; + +static inline u64 rot_insert(u64 x, u64 y, u32 n, u32 mb, u32 me) +{ + if (n) + x = 0 +#ifdef SL + | (x << n) +#endif +#ifdef SR + | (x >> (64 - n)) +#endif + ; + + u64 s = -1; + if (n) + s = 0 +#ifdef SL + | (s << n) +#endif +#ifdef SR + | (s >> (64 - n)) +#endif + ; + + u64 mask = 0; + mask += 1ULL << (63 - mb); + mask += 1ULL << (63 - mb); + mask -= 1ULL << (63 - me); + mask -= (mb > me); + + if (mask & ~s) + return 12345*y; + + return (x & mask) | (y & ~mask); +} + +#define X2(N,B) \ +u64 f_##N##_##B(u64 x, u64 y) { return rot_insert(x,y,N,B,63-N); } \ +u64 g_##N##_##B(u64 x, u64 y) { return rot_insert(y,x,N,B,63-N); } + +#define X1(N) \ +X2(N,0) \ +X2(N,1) \ +X2(N,2) \ +X2(N,7) \ +X2(N,8) \ +X2(N,9) \ +X2(N,15) \ +X2(N,16) \ +X2(N,17) \ +X2(N,23) \ +X2(N,24) \ +X2(N,25) \ +X2(N,29) \ +X2(N,30) \ +X2(N,31) \ +X2(N,32) \ +X2(N,33) \ +X2(N,34) \ +X2(N,39) \ +X2(N,40) \ +X2(N,41) \ +X2(N,47) \ +X2(N,48) \ +X2(N,49) \ +X2(N,55) \ +X2(N,56) \ +X2(N,57) \ +X2(N,61) \ +X2(N,62) \ +X2(N,63) +#define X() \ +X1(0) \ +X1(1) \ +X1(2) \ +X1(7) \ +X1(8) \ +X1(9) \ +X1(15) \ +X1(16) \ +X1(17) \ +X1(23) \ +X1(24) \ +X1(25) \ +X1(29) \ +X1(30) \ +X1(31) \ +X1(32) \ +X1(33) \ +X1(34) \ +X1(39) \ +X1(40) \ +X1(41) \ +X1(47) \ +X1(48) \ +X1(49) \ +X1(55) \ +X1(56) \ +X1(57) \ +X1(61) \ +X1(62) \ +X1(63) + +X() diff --git a/gcc/testsuite/gcc.target/powerpc/rlwimi-0.c b/gcc/testsuite/gcc.target/powerpc/rlwimi-0.c new file mode 100644 index 00000000000..961be199901 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rlwimi-0.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 16485 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 19909 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+blr} 6750 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+mr} 3007 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+mr} 11 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 6420 { target lp64 } } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 6420 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rldimi} 310 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 6110 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rotlwi} 308 } } */ + + +#define SL +#define SR + +#include "rlwimi.h" diff --git a/gcc/testsuite/gcc.target/powerpc/rlwimi-1.c b/gcc/testsuite/gcc.target/powerpc/rlwimi-1.c new file mode 100644 index 00000000000..e2c607b1d45 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rlwimi-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 13977 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 20217 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+blr} 6750 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+mr} 499 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+mr} 11 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 6728 { target lp64 } } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1404 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rldimi} 134 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1270 { target lp64 } } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+mulli} 5324 } } */ + + +#define SL + +#include "rlwimi.h" diff --git a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c new file mode 100644 index 00000000000..62344a95aa0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 14121 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 20217 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+blr} 6750 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+mr} 643 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+mr} 11 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 6728 { target lp64 } } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1692 } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+mulli} 5036 } } */ + + +#define SR + +#include "rlwimi.h" diff --git a/gcc/testsuite/gcc.target/powerpc/rlwimi.h b/gcc/testsuite/gcc.target/powerpc/rlwimi.h new file mode 100644 index 00000000000..c944e2a4b88 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rlwimi.h @@ -0,0 +1,91 @@ +typedef unsigned int u32; + +static inline u32 rot_insert(u32 x, u32 y, u32 n, u32 mb, u32 me) +{ + if (n) + x = 0 +#ifdef SL + | (x << n) +#endif +#ifdef SR + | (x >> (32 - n)) +#endif + ; + + u32 s = -1; + if (n) + s = 0 +#ifdef SL + | (s << n) +#endif +#ifdef SR + | (s >> (32 - n)) +#endif + ; + + u32 mask = 0; + mask += 1U << (31 - mb); + mask += 1U << (31 - mb); + mask -= 1U << (31 - me); + mask -= (mb > me); + + if (mask & ~s) + return 12345*y; + + return (x & mask) | (y & ~mask); +} + +#define X3(N,B,E) \ +u32 f_##N##_##B##_##E(u32 x, u32 y) { return rot_insert(x,y,N,B,E); } \ +u32 g_##N##_##B##_##E(u32 x, u32 y) { return rot_insert(y,x,N,B,E); } + +#define X2(N,B) \ +X3(N,B,0) \ +X3(N,B,1) \ +X3(N,B,2) \ +X3(N,B,7) \ +X3(N,B,8) \ +X3(N,B,9) \ +X3(N,B,15) \ +X3(N,B,16) \ +X3(N,B,17) \ +X3(N,B,23) \ +X3(N,B,24) \ +X3(N,B,25) \ +X3(N,B,29) \ +X3(N,B,30) \ +X3(N,B,31) +#define X1(N) \ +X2(N,0) \ +X2(N,1) \ +X2(N,2) \ +X2(N,7) \ +X2(N,8) \ +X2(N,9) \ +X2(N,15) \ +X2(N,16) \ +X2(N,17) \ +X2(N,23) \ +X2(N,24) \ +X2(N,25) \ +X2(N,29) \ +X2(N,30) \ +X2(N,31) +#define X() \ +X1(0) \ +X1(1) \ +X1(2) \ +X1(7) \ +X1(8) \ +X1(9) \ +X1(15) \ +X1(16) \ +X1(17) \ +X1(23) \ +X1(24) \ +X1(25) \ +X1(29) \ +X1(30) \ +X1(31) + +X() diff --git a/gcc/testsuite/gcc.target/powerpc/rlwinm-0.c b/gcc/testsuite/gcc.target/powerpc/rlwinm-0.c new file mode 100644 index 00000000000..2940b62796a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rlwinm-0.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 6739 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 9730 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+blr} 3375 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 3095 { target lp64 } } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 3197 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 3094 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rotlwi} 154 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+srwi} 13 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+srdi} 12 { target lp64 } } } */ + + +#define SL +#define SR + +#include "rlwinm.h" diff --git a/gcc/testsuite/gcc.target/powerpc/rlwinm-1.c b/gcc/testsuite/gcc.target/powerpc/rlwinm-1.c new file mode 100644 index 00000000000..0fc08a62390 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rlwinm-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 6739 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 9606 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+blr} 3375 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rldic} 2946 { target lp64 } } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 691 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 622 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+slwi} 11 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+slwi} 1 { target lp64 } } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+mulli} 2662 { target ilp32 } } } */ + + +#define SL + +#include "rlwinm.h" diff --git a/gcc/testsuite/gcc.target/powerpc/rlwinm-2.c b/gcc/testsuite/gcc.target/powerpc/rlwinm-2.c new file mode 100644 index 00000000000..4087ac06c2a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rlwinm-2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 6739 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 9466 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+blr} 3375 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rldic} 2840 { target lp64 } } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 833 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 721 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+srwi} 13 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+srdi} 12 { target lp64 } } } */ + +/* { dg-final { scan-assembler-times {(?n)^\s+mulli} 2518 } } */ + + +#define SR + +#include "rlwinm.h" diff --git a/gcc/testsuite/gcc.target/powerpc/rlwinm.h b/gcc/testsuite/gcc.target/powerpc/rlwinm.h new file mode 100644 index 00000000000..d1220e02207 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rlwinm.h @@ -0,0 +1,92 @@ +typedef unsigned int u32; + +static inline u32 rot(u32 x, u32 n, u32 mb, u32 me) +{ + u32 y = x; + + if (n) + x = 0 +#ifdef SL + | (x << n) +#endif +#ifdef SR + | (x >> (32 - n)) +#endif + ; + + u32 s = -1; + if (n) + s = 0 +#ifdef SL + | (s << n) +#endif +#ifdef SR + | (s >> (32 - n)) +#endif + ; + + u32 mask = 0; + mask += 1U << (31 - mb); + mask += 1U << (31 - mb); + mask -= 1U << (31 - me); + mask -= (mb > me); + + if (mask & ~s) + return 12345*y; + + return x & mask; +} + +#define X3(N,B,E) \ +u32 f_##N##_##B##_##E(u32 x) { return rot(x,N,B,E); } \ + +#define X2(N,B) \ +X3(N,B,0) \ +X3(N,B,1) \ +X3(N,B,2) \ +X3(N,B,7) \ +X3(N,B,8) \ +X3(N,B,9) \ +X3(N,B,15) \ +X3(N,B,16) \ +X3(N,B,17) \ +X3(N,B,23) \ +X3(N,B,24) \ +X3(N,B,25) \ +X3(N,B,29) \ +X3(N,B,30) \ +X3(N,B,31) +#define X1(N) \ +X2(N,0) \ +X2(N,1) \ +X2(N,2) \ +X2(N,7) \ +X2(N,8) \ +X2(N,9) \ +X2(N,15) \ +X2(N,16) \ +X2(N,17) \ +X2(N,23) \ +X2(N,24) \ +X2(N,25) \ +X2(N,29) \ +X2(N,30) \ +X2(N,31) +#define X() \ +X1(0) \ +X1(1) \ +X1(2) \ +X1(7) \ +X1(8) \ +X1(9) \ +X1(15) \ +X1(16) \ +X1(17) \ +X1(23) \ +X1(24) \ +X1(25) \ +X1(29) \ +X1(30) \ +X1(31) + +X()