From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 21 Sep 2018 05:37:31 +0000 (+0200)
Subject: README: add migen/litex clarification
X-Git-Tag: 24jan2021_ls180~1601
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=01ae7d4235d141f4965ccaff02d61c76c5ff662a;p=litex.git

README: add migen/litex clarification
---

diff --git a/README b/README
index 31e38820..e167f55b 100644
--- a/README
+++ b/README
@@ -12,6 +12,13 @@
 LiteX is a FPGA design/SoC builder that can be used to build cores, create
 SoCs and full FPGA designs.
 
+LiteX is based on Migen and provides specific building/debugging tools for
+a higher level of abstraction and compatibily with the LiteX core ecosystem.
+
+Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a
+toolbox to create/develop/debug FPGA SoCs in Python.
+
+
 Typical LiteX design flow:
 --------------------------