From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 13 Dec 2021 12:35:02 +0000 (+0000)
Subject: construct an MSRSpec in PortInterfaceBase (not used yet)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=01b6ae3c9a5b03ac4d4d28b6dc14e3e7b729f52b;p=soc.git

construct an MSRSpec in PortInterfaceBase (not used yet)
---

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 51a6abef..7e92e967 100644
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -228,6 +228,7 @@ class PortInterfaceBase(Elaboratable):
         pr = ~pi.priv_mode
         dr = pi.virt_mode   # not yet used
         sf = pi.mode_32bit   # not yet used
+        msr = MSRSpec(pr=pr, dr=dr, sf=sf)
 
         # detect busy "edge"
         busy_delay = Signal()