From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 11 Jul 2020 20:01:47 +0000 (+0100)
Subject: add bigendian mode to helloworld test
X-Git-Tag: div_pipeline~93
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=01bb2bd6a42bbb88ce718127fdd9f47d81a0e189;p=soc.git

add bigendian mode to helloworld test
---

diff --git a/src/soc/config/endian.py b/src/soc/config/endian.py
index 0aaa61c2..eb6e0c3f 100644
--- a/src/soc/config/endian.py
+++ b/src/soc/config/endian.py
@@ -1,5 +1,5 @@
 global bigendian
-bigendian = 1
+bigendian = 0
 
 def set_endian_mode(mode):
     bigendian = mode
diff --git a/src/soc/simple/test/test_microwatt.py b/src/soc/simple/test/test_microwatt.py
index fc2e3f15..1abfa8ea 100644
--- a/src/soc/simple/test/test_microwatt.py
+++ b/src/soc/simple/test/test_microwatt.py
@@ -8,6 +8,8 @@ from nmigen.back.pysim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 
 from soc.simple.issuer import TestIssuer
+from soc.config.endian import bigendian
+
 
 from soc.config.test.test_loadstore import TestMemPspec
 from soc.simple.test.test_core import (setup_regs, check_regs,
@@ -32,11 +34,11 @@ class BinaryTestCase(FHDLTestCase):
 
     @unittest.skip("a bit big")
     def test_binary(self):
-        with Program("1.bin") as program:
+        with Program("1.bin", bigendian) as program:
             self.run_tst_program(program)
 
     def test_binary(self):
-        with Program("hello_world.bin") as program:
+        with Program("hello_world.bin", bigendian) as program:
             self.run_tst_program(program)
 
     def run_tst_program(self, prog):