From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 1 Feb 2016 09:10:20 +0000 (+0100)
Subject: SigMap performance improvement
X-Git-Tag: yosys-0.6~27
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=01bcc5663fa7c65ddbb6c55abebcfc60af8d200b;p=yosys.git

SigMap performance improvement
---

diff --git a/kernel/sigtools.h b/kernel/sigtools.h
index 83ff470d2..4e97bb775 100644
--- a/kernel/sigtools.h
+++ b/kernel/sigtools.h
@@ -242,7 +242,13 @@ struct SigMap
 
 	void set(RTLIL::Module *module)
 	{
-		clear();
+		int bitcount = 0;
+		for (auto &it : module->connections())
+			bitcount += it.first.size();
+
+		database.clear();
+		database.reserve(bitcount);
+
 		for (auto &it : module->connections())
 			add(it.first, it.second);
 	}