From: Eric Botcazou <ebotcazou@libertysurf.fr>
Date: Wed, 4 Jun 2003 07:13:03 +0000 (+0200)
Subject: re PR rtl-optimization/11018 ([SPARC] -mcpu=ultrasparc busts tar-1.13.25)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=01d3224a48291c181104b127a4490379f54b9a31;p=gcc.git

re PR rtl-optimization/11018 ([SPARC] -mcpu=ultrasparc busts tar-1.13.25)

	PR optimization/11018
	* config/sparc/sparc.c (sparc_v8plus_shift): Use which_alternative
	consistently to decide whether the scratch register is really
	required.

From-SVN: r67429
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 31ba84f62e0..5c585961cc1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2003-06-04  Eric Botcazou  <ebotcazou@libertysurf.fr>
+
+	PR optimization/11018
+	* config/sparc/sparc.c (sparc_v8plus_shift): Use which_alternative
+	consistently to decide whether the scratch register is really
+	required.
+
 2003-06-04  Eric Botcazou  <ebotcazou@libertysurf.fr>
 
 	PR optimization/10876
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 24907f146bc..f368e967071 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -3401,7 +3401,7 @@ mem_min_alignment (mem, desired)
 
 
 /* Vectors to keep interesting information about registers where it can easily
-   be got.  We use to use the actual mode value as the bit number, but there
+   be got.  We used to use the actual mode value as the bit number, but there
    are more than 32 modes now.  Instead we use two tables: one indexed by
    hard register number, and one indexed by mode.  */
 
@@ -7969,6 +7969,8 @@ sparc_check_64 (x, insn)
   return 0;
 }
 
+/* Returns assembly code to perform a DImode shift using
+   a 64-bit global or out register on SPARC-V8+.  */
 char *
 sparc_v8plus_shift (operands, insn, opcode)
      rtx *operands;
@@ -7977,8 +7979,11 @@ sparc_v8plus_shift (operands, insn, opcode)
 {
   static char asm_code[60];
 
-  if (GET_CODE (operands[3]) == SCRATCH)
+  /* The scratch register is only required when the destination
+     register is not a 64-bit global or out register.  */
+  if (which_alternative != 2)
     operands[3] = operands[0];
+
   if (GET_CODE (operands[1]) == CONST_INT)
     {
       output_asm_insn ("mov\t%1, %3", operands);
@@ -7992,6 +7997,7 @@ sparc_v8plus_shift (operands, insn, opcode)
     }
 
   strcpy(asm_code, opcode);
+
   if (which_alternative != 2)
     return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
   else
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index c5c95070dd4..ab76c7b8343 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2003-06-04  Eric Botcazou  <ebotcazou@libertysurf.fr>
+
+	* gcc.dg/ultrasp9.c: New test.
+
 2003-06-04  Eric Botcazou  <ebotcazou@libertysurf.fr>
 
 	* gcc.c-torture/compile/20030604-1.c: New test.
diff --git a/gcc/testsuite/gcc.dg/ultrasp9.c b/gcc/testsuite/gcc.dg/ultrasp9.c
new file mode 100644
index 00000000000..885420e0509
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/ultrasp9.c
@@ -0,0 +1,39 @@
+/* PR optimization/11018 */
+/* Originator: <partain@dcs.gla.ac.uk> */
+/* { dg-do run { target sparc*-*-* } } */
+/* { dg-options "-O2 -mcpu=ultrasparc" } */
+
+/* This used to fail on 32-bit Ultrasparc because
+   of broken DImode shift patterns.  */
+
+extern void abort(void);
+
+typedef unsigned long long uint64_t;
+typedef unsigned int size_t;
+
+
+void to_octal (uint64_t value, char *where, size_t size)
+{
+  uint64_t v = value;
+  size_t i = size;
+
+  do
+    {
+      where[--i] = '0' + (v & ((1 << 3) - 1));
+      v >>= 3;
+    }
+  while (i);
+}
+
+
+int main (void)
+{
+  char buf[8];
+
+  to_octal(010644, buf, 6);
+
+  if (buf[1] != '1')
+     abort();
+
+  return 0;
+}