From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 10 Jan 2024 16:40:52 +0000 (+0000)
Subject: bug 676: use dest-mask on sv.addi to get scalar max into vector
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=01d7bd317d33cd5f1b462a981809b674ca0fd559;p=openpower-isa.git

bug 676: use dest-mask on sv.addi to get scalar max into vector
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 57c8fea3..8816cbd5 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -248,7 +248,7 @@ class GPR(dict):
         log("GPR getitem", attr, rnum)
         return self.regfile[rnum]
 
-    def dump(self, printout=True, heading="log"):
+    def dump(self, printout=True, heading="reg"):
         res = []
         for i in range(len(self)):
             res.append(self[i].value)
diff --git a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py
index e5d23189..2206477f 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py
@@ -93,7 +93,7 @@ class DDFFirstTestCase(FHDLTestCase):
                 "mtcrf 128, 0",       # clear CR0
                 "sv.minmax./ff=lt/m=ge 4, *10, 4, 1", # uses r4 as accumulator
                 "sv.svstep/mr 3, 0, 6, 1",  # svstep: get vector dststep
-                "sv.addi/m=1<<r3 *10, 4, 0", # put r4 into vector at r10
+                "sv.addi/dm=1<<r3 *4, 4, 0", # put r4 into vector at r4
                 "sv.creqv *16,*16,*16", # set mask on already-tested
                 "bc 12,0, -0x44"            # CR0 lt bit clear, branch back
                 #"setvl 3,0,4,0,1,1",        # set MVL=4, VL=MIN(MVL,CTR)