From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Fri, 7 Aug 2020 16:10:54 +0000 (+0200)
Subject: examples: Display rdly map
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=01dd0533923cec09d0bc525e8233d82eae893e64;p=gram.git

examples: Display rdly map
---

diff --git a/examples/firmware/main.c b/examples/firmware/main.c
index cd26b73..c9be376 100644
--- a/examples/firmware/main.c
+++ b/examples/firmware/main.c
@@ -67,6 +67,8 @@ void isr(void) {
 int main(void) {
 	const int kNumIterations = 65536;
 	int res, failcnt = 0;
+	uint32_t tmp;
+	volatile uint32_t *ram = 0x10000000;
 	uart_writestr("Firmware launched...\n");
 
 	uart_writestr("DRAM init... ");
@@ -82,6 +84,38 @@ int main(void) {
 	gram_init(&ctx, &profile, (void*)0x10000000, (void*)0x00009000, (void*)0x00008000);
 	uart_writestr("done\n");
 
+	uart_writestr("Rdly\np0: ");
+	for (size_t i = 0; i < 8; i++) {
+		profile2.rdly_p0 = i;
+		gram_load_calibration(&ctx, &profile2);
+		gram_reset_burstdet(&ctx);
+		for (size_t j = 0; j < 128; j++) {
+			tmp = ram[j];
+		}
+		if (gram_read_burstdet(&ctx, 0)) {
+			uart_writestr("1");
+		} else {
+			uart_writestr("0");
+		}
+	}
+	uart_writestr("\n");
+
+	uart_writestr("Rdly\np1: ");
+	for (size_t i = 0; i < 8; i++) {
+		profile2.rdly_p1 = i;
+		gram_load_calibration(&ctx, &profile2);
+		gram_reset_burstdet(&ctx);
+		for (size_t j = 0; j < 128; j++) {
+			tmp = ram[j];
+		}
+		if (gram_read_burstdet(&ctx, 1)) {
+			uart_writestr("1");
+		} else {
+			uart_writestr("0");
+		}
+	}
+	uart_writestr("\n");
+
 	uart_writestr("Auto calibrating... ");
 	res = gram_generate_calibration(&ctx, &profile2);
 	if (res != GRAM_ERR_NONE) {
@@ -100,7 +134,6 @@ int main(void) {
 	uart_writestr("\n");
 
 	uart_writestr("DRAM test... \n");
-	volatile uint32_t *ram = 0x10000000;
 	for (size_t i = 0; i < kNumIterations; i++) {
 		ram[i] = 0xDEAF0000 | i*4;
 	}