From: Richard Kenner Date: Sun, 27 Sep 1992 17:05:40 +0000 (-0400) Subject: (subsi3): Don't bother calling negate_rtx for constant; we shouldn't be called with... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=01def76468d36fe7524eca8b54feef5482eacb3e;p=gcc.git (subsi3): Don't bother calling negate_rtx for constant; we shouldn't be called with a constant. (subsi3): Don't bother calling negate_rtx for constant; we shouldn't be called with a constant. (maskir patterns): Don't mention an operand before it is used; use operand number 1 for operand with '0' constraint. (allocate_stack): Use reg_or_short_operand for predicate of allocation amount; use negate_rtx and always make a PLUS. From-SVN: r2262 --- diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 9da114a4647..cbcb156ae0e 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -259,15 +259,7 @@ (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") (match_operand:SI 2 "reg_or_cint_operand" "")))] "" - " -{ - if (GET_CODE (operands[2]) == CONST_INT) - { - emit_insn (gen_addsi3 (operands[0], operands[1], - negate_rtx (SImode, operands[2]))); - DONE; - } -}") + "") ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] ;; instruction and some auxiliary computations. Then we just have a single @@ -965,98 +957,98 @@ (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) - (match_operand:SI 2 "gpc_reg_operand" "0")) - (and:SI (match_dup 1) + (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) + (match_operand:SI 1 "gpc_reg_operand" "0")) + (and:SI (match_dup 2) (match_operand:SI 3 "gpc_reg_operand" "r"))))] "" - "maskir %0,%3,%1") + "maskir %0,%3,%2") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") - (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) - (match_operand:SI 2 "gpc_reg_operand" "0")) + (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) + (match_operand:SI 1 "gpc_reg_operand" "0")) (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") - (match_dup 1))))] + (match_dup 2))))] "" - "maskir %0,%3,%1") + "maskir %0,%3,%2") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (ior:SI (and:SI (match_dup 1) + (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") (match_operand:SI 3 "gpc_reg_operand" "r")) - (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) - (match_operand:SI 2 "gpc_reg_operand" "0"))))] + (and:SI (not:SI (match_dup 2)) + (match_operand:SI 1 "gpc_reg_operand" "0"))))] "" - "maskir %0,%3,%1") + "maskir %0,%3,%2") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") - (match_dup 1)) - (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) - (match_operand:SI 2 "gpc_reg_operand" "0"))))] + (match_operand:SI 2 "gpc_reg_operand" "r")) + (and:SI (not:SI (match_dup 2)) + (match_operand:SI 1 "gpc_reg_operand" "0"))))] "" - "maskir %0,%3,%1") + "maskir %0,%3,%2") (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) - (match_operand:SI 2 "gpc_reg_operand" "0")) - (and:SI (match_dup 1) + (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) + (match_operand:SI 1 "gpc_reg_operand" "0")) + (and:SI (match_dup 2) (match_operand:SI 3 "gpc_reg_operand" "r"))) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (ior:SI (and:SI (not:SI (match_dup 1)) (match_dup 2)) - (and:SI (match_dup 1) (match_dup 3))))] + (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) + (and:SI (match_dup 2) (match_dup 3))))] "" - "maskir. %0,%3,%1" + "maskir. %0,%3,%2" [(set_attr "type" "compare")]) (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) - (match_operand:SI 2 "gpc_reg_operand" "0")) + (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) + (match_operand:SI 1 "gpc_reg_operand" "0")) (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") - (match_dup 1))) + (match_dup 2))) (const_int 0))) (set (match_operand:SI 0 "register_operand" "=r") - (ior:SI (and:SI (not:SI (match_dup 1)) (match_dup 2)) - (and:SI (match_dup 3) (match_dup 1))))] + (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) + (and:SI (match_dup 3) (match_dup 2))))] "" - "maskir. %0,%3,%1" + "maskir. %0,%3,%2" [(set_attr "type" "compare")]) (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (ior:SI (and:SI (match_dup 1) + (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") (match_operand:SI 3 "gpc_reg_operand" "r")) - (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) - (match_operand:SI 2 "gpc_reg_operand" "0"))) + (and:SI (not:SI (match_dup 2)) + (match_operand:SI 1 "gpc_reg_operand" "0"))) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (ior:SI (and:SI (match_dup 1) (match_dup 3)) - (and:SI (not:SI (match_dup 1)) (match_dup 2))))] + (ior:SI (and:SI (match_dup 2) (match_dup 3)) + (and:SI (not:SI (match_dup 2)) (match_dup 1))))] "" - "maskir. %0,%3,%1" + "maskir. %0,%3,%2" [(set_attr "type" "compare")]) (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") - (match_dup 1)) - (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) - (match_operand:SI 2 "gpc_reg_operand" "0"))) + (match_operand:SI 2 "gpc_reg_operand" "r")) + (and:SI (not:SI (match_dup 2)) + (match_operand:SI 1 "gpc_reg_operand" "0"))) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (ior:SI (and:SI (match_dup 3) (match_dup 1)) - (and:SI (not:SI (match_dup 1)) (match_dup 2))))] + (ior:SI (and:SI (match_dup 3) (match_dup 2)) + (and:SI (not:SI (match_dup 2)) (match_dup 1))))] "" - "maskir. %0,%3,%1" + "maskir. %0,%3,%2" [(set_attr "type" "compare")]) ;; Rotate and shift insns, in all their variants. These support shifts, @@ -2894,14 +2886,15 @@ (define_expand "allocate_stack" [(set (reg:SI 1) - (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_cint_operand" "")))] + (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_short_operand" "")))] "" " { rtx chain = gen_reg_rtx (SImode); rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx); emit_move_insn (chain, stack_bot); - emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, operands[0])); + emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, + negate_rtx (SImode, operands[0]))); emit_move_insn (stack_bot, chain); DONE; }")