From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 1 Jul 2020 15:51:10 +0000 (+0100)
Subject: trap test check results
X-Git-Tag: div_pipeline~186
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=01e4738743a137f652e1cb9b34df3b504e58de54;p=soc.git

trap test check results
---

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index 7c46bf37..4b43b47e 100644
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -122,11 +122,11 @@ class ALUHelpers:
             print ("extra inputs: so", so)
             yield alu.p.data_i.xer_so.eq(so)
 
-    def set_fast_msr(alu, dec2, inp):
+    def set_msr(alu, dec2, inp):
         if 'msr' in inp:
             yield alu.p.data_i.msr.eq(inp['msr'])
 
-    def set_fast_cia(alu, dec2, inp):
+    def set_cia(alu, dec2, inp):
         if 'cia' in inp:
             yield alu.p.data_i.cia.eq(inp['cia'])
 
@@ -166,12 +166,15 @@ class ALUHelpers:
         if spr2_valid:
             res['spr2'] = yield alu.n.data_o.spr2.data
 
-    def get_fast_nia(res, alu, dec2):
+    def get_cia(res, alu, dec2):
+        res['cia'] = yield alu.p.data_i.cia
+
+    def get_nia(res, alu, dec2):
         nia_valid = yield alu.n.data_o.nia.ok
         if nia_valid:
             res['nia'] = yield alu.n.data_o.nia.data
 
-    def get_fast_msr(res, alu, dec2):
+    def get_msr(res, alu, dec2):
         msr_valid = yield alu.n.data_o.msr.ok
         if msr_valid:
             res['msr'] = yield alu.n.data_o.msr.data
diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py
index 8c32fc73..4f1af455 100644
--- a/src/soc/fu/trap/test/test_pipe_caller.py
+++ b/src/soc/fu/trap/test/test_pipe_caller.py
@@ -44,8 +44,8 @@ def set_alu_inputs(alu, dec2, sim):
     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
 
-    yield from ALUHelpers.set_fast_cia(alu, dec2, inp)
-    yield from ALUHelpers.set_fast_msr(alu, dec2, inp)
+    yield from ALUHelpers.set_cia(alu, dec2, inp)
+    yield from ALUHelpers.set_msr(alu, dec2, inp)
 
 
 # This test bench is a bit different than is usual. Initially when I
@@ -201,8 +201,8 @@ class TestRunner(FHDLTestCase):
         yield from ALUHelpers.get_int_o(res, alu, dec2)
         yield from ALUHelpers.get_fast_spr1(res, alu, dec2)
         yield from ALUHelpers.get_fast_spr2(res, alu, dec2)
-        yield from ALUHelpers.get_fast_nia(res, alu, dec2)
-        yield from ALUHelpers.get_fast_msr(res, alu, dec2)
+        yield from ALUHelpers.get_nia(res, alu, dec2)
+        yield from ALUHelpers.get_msr(res, alu, dec2)
 
         print ("output", res)
 
@@ -210,7 +210,8 @@ class TestRunner(FHDLTestCase):
         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
         yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
-        yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
+        ALUHelpers.get_sim_cia(sim_o, sim, dec2)
+        ALUHelpers.get_sim_msr(sim_o, sim, dec2)
 
         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
         ALUHelpers.check_xer_ov(self, res, sim_o, code)