From: David Shah <dave@ds0.me>
Date: Mon, 21 Jan 2019 12:33:47 +0000 (+0000)
Subject: ecp5: Increase threshold for ALU mapping
X-Git-Tag: yosys-0.9~291^2~8
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=01ea72f53a9707d741a1178d0ac4c4f69d6b65db;p=yosys.git

ecp5: Increase threshold for ALU mapping

Signed-off-by: David Shah <dave@ds0.me>
---

diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v
index 1094c5f8a..eb7947601 100644
--- a/techlibs/ecp5/arith_map.v
+++ b/techlibs/ecp5/arith_map.v
@@ -33,7 +33,7 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
 	input CI, BI;
 	output [Y_WIDTH-1:0] CO;
 
-	wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+	wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
 
 	wire [Y_WIDTH-1:0] A_buf, B_buf;
 	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));