From: Samuel Pitoiset Date: Tue, 21 Jan 2020 08:47:18 +0000 (+0100) Subject: aco: fix wrong IR in nir_intrinsic_load_barycentric_at_sample X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=01f0bef71e60a9853ce7854288678ec15adde79f;p=mesa.git aco: fix wrong IR in nir_intrinsic_load_barycentric_at_sample Only GFX6 was affected, my mistake. The total number of SGPR operands should be 4 when we want to create a vec4. Fixes: dbdf3b3ef97 ("aco: implement nir_intrinsic_load_barycentric_at_sample on GFX6") Signed-off-by: Samuel Pitoiset Reviewed-by: Daniel Schürmann Part-of: --- diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 22d6e3f341f..47e1737b5d9 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -5579,7 +5579,7 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr) uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32); - Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), private_segment_buffer, Operand(rsrc_conf)); + Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), private_segment_buffer, Operand(0u), Operand(rsrc_conf)); addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr); addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), addr, Operand(0u));