From: lkcl Date: Sat, 22 Oct 2022 15:16:39 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~56 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=01f47ea74d28b763e12e4564eaafe9d6869f52e0;p=libreriscv.git --- diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn index ca6065eb0..1f7de4325 100644 --- a/openpower/sv/biginteger.mdwn +++ b/openpower/sv/biginteger.mdwn @@ -53,18 +53,15 @@ operations. **DRAFT** -`dsld` and `dsrd` are similar to v3.0 `sld`, and -is Z23-Form in "overwrite" on RT. +`dsld` and `dsrd` are similar to v3.0 `sld`, and are VA2-Form -|0.....5|6..10|11..15|16..20|21.22|23..30|31| -|-------|-----|------|------|-----|------|--| -| EXT04 | RT | RA | RB | sm | XO |Rc| +|0.....5|6..10|11..15|16..20|21..25|26..30|31| +|-------|-----|------|------|------|------|--| +| EXT04 | RT | RA | RB | RC | XO |Rc| Both instructions take two 64-bit sources, concatenate them together then extract 64 bits from it, the offset -location determined by a third source. So as to avoid -costly 4-reg (VA-Form) a 2-bit mode `sm` gives four -potential overwrite and zero-source options instead. +location determined by a third source. # maddedu @@ -182,7 +179,8 @@ see Power ISA v3.1, Book III, Appendix D, Table 13 (sheet 7 of 8), p1357. Proposed is the addition of `maddedu` (**DRAFT, NOT APPROVED**) in `110010` and `divmod2du` in `110100` -|110000|110001 |110010 |110011|110100 |110101|110110|110111| -|------|-------|----------|------|-------------|------|------|------| -|maddhd|maddhdu|**maddedu**|maddld|**divmod2du**|rsvd |rsvd |rsvd | +| v > | 000| 001 | 010 | 011| 100 | 101| 110| 111| +|-----|------|-------|----------|------|-------------|------|------|------| +| 110 |maddhd|maddhdu|**maddedu**|maddld|**divmod2du**|rsvd |rsvd |rsvd | +| 010 |dsld |dsld. |dsrd |dsrd. |mtvsrbmi |mtvsrbmi |vsldbi|vmsumcud|