From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 Jun 2019 07:42:44 +0000 (+0100)
Subject: add inc_offs function to be used for vl/subvl loops
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=01f4c1f1857b4d34f7186897e05ac83a49926e11;p=riscv-isa-sim.git

add inc_offs function to be used for vl/subvl loops
---

diff --git a/riscv/sv.cc b/riscv/sv.cc
index cf70568..ac98c69 100644
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -20,6 +20,29 @@ uint8_t maxelwidth(uint8_t wid1, uint8_t wid2)
     return std::max(wid1, wid2);
 }
 
+/* increments the offset and sub-offset appropriately in a FSM-based
+   version of a twin-nested for-loop:
+   for (offs = 0; offs < vlen; offs++) {
+     for (suboffs = 0; suboffs < subvl; suboffs++) {
+     ... doooo stuuuuff (python would use "yield" here)
+     }
+     suboffs = 0; // reset to zero after "loop"
+   }
+*/
+bool inc_offs(int vlen, int subvl, int &offs, int &suboffs)
+{
+    suboffs++;
+    if (suboffs < subvl) {
+        return true; // double-nested loop can continue
+    }
+    suboffs = 0; // reset the sub-offs
+    offs += 1; // increment the outer (VL) loop instead
+    if (offs < vlen) {
+        return true; // also can continue
+    }
+    return false; // should not continue, however let FN deal with it
+}
+
 sv_insn_t::sv_insn_t(processor_t *pr, bool _sv_enabled,
             insn_bits_t bits, unsigned int f,
             int _xlen, int _src_flen, int _dest_flen,
diff --git a/riscv/sv.h b/riscv/sv.h
index fed8b6f..be96c8c 100644
--- a/riscv/sv.h
+++ b/riscv/sv.h
@@ -119,4 +119,6 @@ typedef struct {
 #define SV_CFG_BANK (0x7)
 #define SV_CFG_SIZE (0x3<<3)
 
+bool inc_offs(int vlen, int subvl, int &offs, int &suboffs);
+
 #endif