From: Tim Newsome <tim@sifive.com>
Date: Thu, 29 Sep 2016 18:24:04 +0000 (-0700)
Subject: Update trigger behavior. (#70)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=02027ca74cb904ee691b7b7d9b03c46f3c1f49ac;p=riscv-isa-sim.git

Update trigger behavior. (#70)

M-mode writes to tdata1 with dmode set are ignored instead of raising an
exception.
Add the same behavior for tdata2.
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 1a41f60..47a3a66 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -419,7 +419,7 @@ void processor_t::set_csr(int which, reg_t val)
       {
         mcontrol_t *mc = &state.mcontrol[state.tselect];
         if (mc->dmode && !state.dcsr.cause) {
-          throw trap_illegal_instruction();
+          break;
         }
         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
         mc->select = get_field(val, MCONTROL_SELECT);
@@ -443,6 +443,9 @@ void processor_t::set_csr(int which, reg_t val)
       }
       break;
     case CSR_TDATA2:
+      if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
+        break;
+      }
       if (state.tselect < state.num_triggers) {
         state.tdata2[state.tselect] = val;
       }