From: Yunsup Lee <yunsup@cs.berkeley.edu>
Date: Thu, 7 Apr 2011 05:44:57 +0000 (-0700)
Subject: [opcodes,pk,sim,xcc] fix utidx - add rd
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=02166b26916d0b2d5303ed6e9b07cdffb435cfce;p=riscv-isa-sim.git

[opcodes,pk,sim,xcc] fix utidx - add rd
---

diff --git a/riscv/execute.h b/riscv/execute.h
index 79a13f8..373a4e0 100644
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -1530,7 +1530,7 @@ switch((insn.bits >> 0x0) & 0x7f)
       }
       case 0x3:
       {
-        if((insn.bits & 0xffffffff) == 0x1f7)
+        if((insn.bits & 0x7ffffff) == 0x1f7)
         {
           #include "insns/utidx.h"
           break;