From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 20 Jun 2019 17:04:42 +0000 (-0700)
Subject: Fix sign extension when sign is 1'bx
X-Git-Tag: yosys-0.9~58^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0221f3e1c5b427678c5679027ee47ec7c0b8321d;p=yosys.git

Fix sign extension when sign is 1'bx
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index a09f4a0d1..95a24c93f 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -3437,7 +3437,7 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
 
 	if (width_ < width) {
 		RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
-		if (!is_signed)
+		if (padding != RTLIL::State::Sx && !is_signed)
 			padding = RTLIL::State::S0;
 		while (width_ < width)
 			append(padding);