From: Steve Chamberlain Date: Sun, 1 Dec 1991 02:29:45 +0000 (+0000) Subject: Initial revision X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0227e9187ba62196cafdb14b5306d93e5cf3ed00;p=binutils-gdb.git Initial revision --- diff --git a/include/aout/encap.h b/include/aout/encap.h new file mode 100644 index 00000000000..cebedf38336 --- /dev/null +++ b/include/aout/encap.h @@ -0,0 +1,135 @@ +/* Yet Another Try at encapsulating bsd object files in coff. + Copyright (C) 1988, 1989, 1991 Free Software Foundation, Inc. + Written by Pace Willisson 12/9/88 + + This file is obsolete. It needs to be converted to just define a bunch + of stuff that BFD can use to do coff-encapsulated files. --gnu@cygnus.com + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* + * We only use the coff headers to tell the kernel + * how to exec the file. Therefore, the only fields that need to + * be filled in are the scnptr and vaddr for the text and data + * sections, and the vaddr for the bss. As far as coff is concerned, + * there is no symbol table, relocation, or line numbers. + * + * A normal bsd header (struct exec) is placed after the coff headers, + * and before the real text. I defined a the new fields 'a_machtype' + * and a_flags. If a_machtype is M_386, and a_flags & A_ENCAP is + * true, then the bsd header is preceeded by a coff header. Macros + * like N_TXTOFF and N_TXTADDR use this field to find the bsd header. + * + * The only problem is to track down the bsd exec header. The + * macros HEADER_OFFSET, etc do this. + */ + +#define N_FLAGS_COFF_ENCAPSULATE 0x20 /* coff header precedes bsd header */ + +/* Describe the COFF header used for encapsulation. */ + +struct coffheader +{ + /* filehdr */ + unsigned short f_magic; + unsigned short f_nscns; + long f_timdat; + long f_symptr; + long f_nsyms; + unsigned short f_opthdr; + unsigned short f_flags; + /* aouthdr */ + short magic; + short vstamp; + long tsize; + long dsize; + long bsize; + long entry; + long text_start; + long data_start; + struct coffscn + { + char s_name[8]; + long s_paddr; + long s_vaddr; + long s_size; + long s_scnptr; + long s_relptr; + long s_lnnoptr; + unsigned short s_nreloc; + unsigned short s_nlnno; + long s_flags; + } scns[3]; +}; + +/* Describe some of the parameters of the encapsulation, + including how to find the encapsulated BSD header. */ + +/* FIXME, this is dumb. The same tools can't handle a.outs for different + architectures, just because COFF_MAGIC is different; so you need a + separate GNU nm for every architecture!!? Unfortunately, it needs to + be this way, since the COFF_MAGIC value is determined by the kernel + we're trying to fool here. */ + +#define COFF_MAGIC_I386 0514 /* I386MAGIC */ +#define COFF_MAGIC_M68K 0520 /* MC68MAGIC */ +#define COFF_MAGIC_A29K 0x17A /* Used by asm29k cross-tools */ + +#ifdef COFF_MAGIC +short __header_offset_temp; +#define HEADER_OFFSET(f) \ + (__header_offset_temp = 0, \ + fread ((char *)&__header_offset_temp, sizeof (short), 1, (f)), \ + fseek ((f), -sizeof (short), 1), \ + __header_offset_temp==COFF_MAGIC ? sizeof(struct coffheader) : 0) +#else +#define HEADER_OFFSET(f) 0 +#endif + +#define HEADER_SEEK(f) (fseek ((f), HEADER_OFFSET((f)), 1)) + +/* Describe the characteristics of the BSD header + that appears inside the encapsulation. */ + +/* Encapsulated coff files that are linked ZMAGIC have a text segment + offset just past the header (and a matching TXTADDR), excluding + the headers from the text segment proper but keeping the physical + layout and the virtual memory layout page-aligned. + + Non-encapsulated a.out files that are linked ZMAGIC have a text + segment that starts at 0 and an N_TXTADR similarly offset to 0. + They too are page-aligned with each other, but they include the + a.out header as part of the text. + + The _N_HDROFF gets sizeof struct exec added to it, so we have + to compensate here. See . */ + +#undef _N_HDROFF +#undef N_TXTADDR +#undef N_DATADDR + +#define _N_HDROFF(x) ((N_FLAGS(x) & N_FLAGS_COFF_ENCAPSULATE) ? \ + sizeof (struct coffheader) : 0) + +/* Address of text segment in memory after it is loaded. */ +#define N_TXTADDR(x) \ + ((N_FLAGS(x) & N_FLAGS_COFF_ENCAPSULATE) ? \ + sizeof (struct coffheader) + sizeof (struct exec) : 0) +#define SEGMENT_SIZE 0x400000 + +#define N_DATADDR(x) \ + ((N_FLAGS(x) & N_FLAGS_COFF_ENCAPSULATE) ? \ + (SEGMENT_SIZE + ((N_TXTADDR(x)+(x).a_text-1) & ~(SEGMENT_SIZE-1))) : \ + (N_TXTADDR(x)+(x).a_text)) diff --git a/include/aout/host.h b/include/aout/host.h new file mode 100644 index 00000000000..5d3488a62ec --- /dev/null +++ b/include/aout/host.h @@ -0,0 +1,22 @@ +/* Parameters about the a.out format, based on the host system on which + the program is compiled. */ + +/* Address of data segment in memory after it is loaded. + It is up to you to define SEGMENT_SIZE + on machines not listed here. */ +#ifndef SEGMENT_SIZE +#if defined(hp300) || defined(pyr) +#define SEGMENT_SIZE page_size +#endif +#ifdef sony +#define SEGMENT_SIZE 0x1000 +#endif /* Sony. */ +#ifdef is68k +#define SEGMENT_SIZE 0x20000 +#endif +#if defined(m68k) && defined(PORTAR) +#define PAGE_SIZE 0x400 +#define SEGMENT_SIZE PAGE_SIZE +#endif +#endif /*!defined(SEGMENT_SIZE)*/ + diff --git a/include/aout/hp.h b/include/aout/hp.h new file mode 100644 index 00000000000..dbd2af9ec44 --- /dev/null +++ b/include/aout/hp.h @@ -0,0 +1,82 @@ +/* Special version of for use under hp-ux. + Copyright 1988, 1991 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* THIS FILE IS OBSOLETE. It needs to be revised as a variant "external" + a.out format for use with BFD. */ + +/* The `exec' structure and overall layout must be close to HP's when + we are running on an HP system, otherwise we will not be able to + execute the resulting file. */ + +/* Allow this file to be included twice. */ +#ifndef __GNU_EXEC_MACROS__ + +struct exec +{ + unsigned short a_machtype; /* machine type */ + unsigned short a_magic; /* magic number */ + unsigned long a_spare1; + unsigned long a_spare2; + unsigned long a_text; /* length of text, in bytes */ + unsigned long a_data; /* length of data, in bytes */ + unsigned long a_bss; /* length of uninitialized data area for file, in bytes */ + unsigned long a_trsize; /* length of relocation info for text, in bytes */ + unsigned long a_drsize; /* length of relocation info for data, in bytes */ + unsigned long a_spare3; /* HP = pascal interface size */ + unsigned long a_spare4; /* HP = symbol table size */ + unsigned long a_spare5; /* HP = debug name table size */ + unsigned long a_entry; /* start address */ + unsigned long a_spare6; /* HP = source line table size */ + unsigned long a_spare7; /* HP = value table size */ + unsigned long a_syms; /* length of symbol table data in file, in bytes */ + unsigned long a_spare8; +}; + +/* Tell a.out.gnu.h not to define `struct exec'. */ +#define __STRUCT_EXEC_OVERRIDE__ + +#include "../a.out.gnu.h" + +#undef N_MAGIC +#undef N_MACHTYPE +#undef N_FLAGS +#undef N_SET_INFO +#undef N_SET_MAGIC +#undef N_SET_MACHTYPE +#undef N_SET_FLAGS + +#define N_MAGIC(exec) ((exec) . a_magic) +#define N_MACHTYPE(exec) ((exec) . a_machtype) +#define N_SET_MAGIC(exec, magic) (((exec) . a_magic) = (magic)) +#define N_SET_MACHTYPE(exec, machtype) (((exec) . a_machtype) = (machtype)) + +#undef N_BADMAG +#define N_BADMAG(x) ((_N_BADMAG (x)) || (_N_BADMACH (x))) + +#define _N_BADMACH(x) \ +(((N_MACHTYPE (x)) != HP9000S200_ID) && \ + ((N_MACHTYPE (x)) != HP98x6_ID)) + +#define HP98x6_ID 0x20A +#define HP9000S200_ID 0x20C + +#undef _N_HDROFF +#define _N_HDROFF(x) (SEGMENT_SIZE - (sizeof (struct exec))) + +#define SEGMENT_SIZE 0x1000 + +#endif /* __GNU_EXEC_MACROS__ */ diff --git a/include/aout/reloc.h b/include/aout/reloc.h new file mode 100644 index 00000000000..1811b73ff9d --- /dev/null +++ b/include/aout/reloc.h @@ -0,0 +1,66 @@ +/* reloc.h -- Header file for relocation information. + Copyright 1989-1991 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* Relocation types for a.out files using reloc_info_extended + (SPARC and AMD 29000). */ + +#ifndef _RELOC_H_READ_ +#define _RELOC_H_READ_ 1 + +enum reloc_type + { + RELOC_8, RELOC_16, RELOC_32, /* simple relocations */ + RELOC_DISP8, RELOC_DISP16, RELOC_DISP32, /* pc-rel displacement */ + RELOC_WDISP30, RELOC_WDISP22, + RELOC_HI22, RELOC_22, + RELOC_13, RELOC_LO10, + RELOC_SFA_BASE, RELOC_SFA_OFF13, + RELOC_BASE10, RELOC_BASE13, RELOC_BASE22, /* P.I.C. (base-relative) */ + RELOC_PC10, RELOC_PC22, /* for some sort of pc-rel P.I.C. (?) */ + RELOC_JMP_TBL, /* P.I.C. jump table */ + RELOC_SEGOFF16, /* reputedly for shared libraries somehow */ + RELOC_GLOB_DAT, RELOC_JMP_SLOT, RELOC_RELATIVE, + RELOC_11, + RELOC_WDISP2_14, + RELOC_WDISP19, + RELOC_HHI22, + RELOC_HLO10, + + /* 29K relocation types */ + RELOC_JUMPTARG, RELOC_CONST, RELOC_CONSTH, + + RELOC_WDISP14, RELOC_WDISP21, + + NO_RELOC + }; + +#define RELOC_TYPE_NAMES \ +"8", "16", "32", "DISP8", \ +"DISP16", "DISP32", "WDISP30", "WDISP22", \ +"HI22", "22", "13", "LO10", \ +"SFA_BASE", "SFAOFF13", "BASE10", "BASE13", \ +"BASE22", "PC10", "PC22", "JMP_TBL", \ +"SEGOFF16", "GLOB_DAT", "JMP_SLOT", "RELATIVE", \ +"11", "WDISP2_14", "WDISP19", "HHI22", \ +"HLO10", \ +"JUMPTARG", "CONST", "CONSTH", "WDISP14", \ +"WDISP21", \ +"NO_RELOC" + +#endif /* _RELOC_H_READ_ */ + +/* end of reloc.h */ diff --git a/include/aout/sun4.h b/include/aout/sun4.h new file mode 100644 index 00000000000..5ad4845e0d0 --- /dev/null +++ b/include/aout/sun4.h @@ -0,0 +1,30 @@ +/* SPARC-specific values for a.out files */ + +#define PAGE_SIZE 0x2000 /* 8K. aka NBPG in */ +/* Note that some SPARCs have 4K pages, some 8K, some others. */ + +#define SEG_SIZE_SPARC PAGE_SIZE +#define SEG_SIZE_SUN3 0x20000 /* Resolution of r/w protection hw */ + +#define TEXT_START_ADDR PAGE_SIZE /* Location 0 is not accessible */ +#define N_HEADER_IN_TEXT(x) 1 + +/* Non-default definitions of the accessor macros... */ + +/* Segment size varies on Sun-3 versus Sun-4. */ + +#define N_SEGSIZE(x) (N_MACHTYPE(x) == M_SPARC? SEG_SIZE_SPARC: \ + N_MACHTYPE(x) == M_68020? SEG_SIZE_SUN3: \ + /* Guess? */ PAGE_SIZE) + +/* Virtual Address of text segment from the a.out file. For OMAGIC, + (almost always "unlinked .o's" these days), should be zero. + Sun added a kludge so that shared libraries linked ZMAGIC get + an address of zero if a_entry (!!!) is lower than the otherwise + expected text address. These kludges have gotta go! + For linked files, should reflect reality if we know it. */ + +#define N_TXTADDR(x) \ + (N_MAGIC(x)==OMAGIC? 0 \ + : (N_MAGIC(x) == ZMAGIC && (x).a_entry < TEXT_START_ADDR)? 0 \ + : TEXT_START_ADDR+EXEC_BYTES_SIZE) diff --git a/include/coff/a29k.h b/include/coff/a29k.h new file mode 100644 index 00000000000..8042d51fb3a --- /dev/null +++ b/include/coff/a29k.h @@ -0,0 +1,305 @@ +/* COFF spec for AMD 290*0 + Contributed by David Wood @ New York University. + */ + +#ifndef AMD +# define AMD +#endif + +/****************************************************************/ + +/* +** File Header and related definitions +*/ + +struct external_filehdr +{ + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ +}; + +#define FILHDR struct external_filehdr +#define FILHSZ sizeof (FILHDR) + +/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/ + +/* +** Magic numbers for Am29000 +** (AT&T will assign the "real" magic number) +*/ + +#define SIPFBOMAGIC 0572 /* Am29000 (Byte 0 is MSB) */ +#define SIPRBOMAGIC 0573 /* Am29000 (Byte 0 is LSB) */ + + +#define A29K_MAGIC_BIG SIPFBOMAGIC +#define A29K_MAGIC_LITTLE SIPRBOMAGIC +#define A29KBADMAG(x) (((x).f_magic!=A29K_MAGIC_BIG) && \ + ((x).f_magic!=A29K_MAGIC_LITTLE)) + +#define OMAGIC A29K_MAGIC_BIG +/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/ + +/* +** File header flags currently known to us. +** +** Am29000 will use the F_AR32WR and F_AR32W flags to indicate +** the byte ordering in the file. +*/ + +/*--------------------------------------------------------------*/ + +/* +** Optional (a.out) header +*/ + +typedef struct external_aouthdr +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ +} AOUTHDR; + +#define AOUTSZ (sizeof(AOUTHDR)) +#define AOUTHDRSZ (sizeof(AOUTHDR)) + +/* aouthdr magic numbers */ +#define NMAGIC 0410 /* separate i/d executable */ +#define SHMAGIC 0406 /* NYU/Ultra3 shared data executable + (writable text) */ + +#define _ETEXT "_etext" + +/*--------------------------------------------------------------*/ + +/* +** Section header and related definitions +*/ + +struct external_scnhdr +{ + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries*/ + char s_flags[4]; /* flags */ +}; + +#define SCNHDR struct external_scnhdr +#define SCNHSZ sizeof (SCNHDR) + +/* + * names of "special" sections + */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" + +/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/ + +/* +** Section types - with additional section type for global +** registers which will be relocatable for the Am29000. +** +** In instances where it is necessary for a linker to produce an +** output file which contains text or data not based at virtual +** address 0, e.g. for a ROM, then the linker should accept +** address base information as command input and use PAD sections +** to skip over unused addresses. +*/ + +#define STYP_BSSREG 0x1200 /* Global register area (like STYP_INFO) */ +#define STYP_ENVIR 0x2200 /* Environment (like STYP_INFO) */ +#define STYP_ABS 0x4000 /* Absolute (allocated, not reloc, loaded) */ +#define STYP_LIT 0x8020 /* Literal data (like STYP_TEXT) */ + +/*--------------------------------------------------------------*/ + +/* +** Relocation information declaration and related definitions +*/ + +struct external_reloc { + char r_vaddr[4]; /* (virtual) address of reference */ + char r_symndx[4]; /* index into symbol table */ + char r_type[2]; /* relocation type */ +}; + +#define RELOC struct external_reloc +#define RELSZ 10 /* sizeof (RELOC) */ + +/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/ + +/* +** Relocation types for the Am29000 +*/ + +#define R_ABS 0 /* reference is absolute */ + +#define R_IREL 030 /* instruction relative (jmp/call) */ +#define R_IABS 031 /* instruction absolute (jmp/call) */ +#define R_ILOHALF 032 /* instruction low half (const) */ +#define R_IHIHALF 033 /* instruction high half (consth) part 1 */ +#define R_IHCONST 034 /* instruction high half (consth) part 2 */ + /* constant offset of R_IHIHALF relocation */ +#define R_BYTE 035 /* relocatable byte value */ +#define R_HWORD 036 /* relocatable halfword value */ +#define R_WORD 037 /* relocatable word value */ + +#define R_IGLBLRC 040 /* instruction global register RC */ +#define R_IGLBLRA 041 /* instruction global register RA */ +#define R_IGLBLRB 042 /* instruction global register RB */ + +/* +NOTE: +All the "I" forms refer to 29000 instruction formats. The linker is +expected to know how the numeric information is split and/or aligned +within the instruction word(s). R_BYTE works for instructions, too. + +If the parameter to a CONSTH instruction is a relocatable type, two +relocation records are written. The first has an r_type of R_IHIHALF +(33 octal) and a normal r_vaddr and r_symndx. The second relocation +record has an r_type of R_IHCONST (34 octal), a normal r_vaddr (which +is redundant), and an r_symndx containing the 32-bit constant offset +to the relocation instead of the actual symbol table index. This +second record is always written, even if the constant offset is zero. +The constant fields of the instruction are set to zero. +*/ + +/*--------------------------------------------------------------*/ + +/* +** Line number entry declaration and related definitions +*/ + +struct external_lineno +{ + union { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } l_addr; + char l_lnno[2]; /* line number */ +}; + +#define LINENO struct external_lineno +#define LINESZ 6 /* sizeof (LINENO) */ + +/*--------------------------------------------------------------*/ + +/* +** Symbol entry declaration and related definitions +*/ + +#define E_SYMNMLEN 8 /* Number of characters in a symbol name */ + +struct external_syment +{ + union { + char e_name[E_SYMNMLEN]; + struct { + char e_zeroes[4]; + char e_offset[4]; + } e; + } e; + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; +}; + +#define SYMENT struct external_syment +#define SYMESZ sizeof(SYMENT) + +/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/ + +/* +** Storage class definitions - new classes for global registers. +*/ + +#define C_GLBLREG 19 /* global register */ +#define C_EXTREG 20 /* external global register */ +#define C_DEFREG 21 /* ext. def. of global register */ + + +/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/ + +/* +** Derived symbol mask/shifts. +*/ + +#define N_BTMASK (0xf) +#define N_BTSHFT (4) +#define N_TMASK (0x30) +#define N_TSHIFT (2) + +/*--------------------------------------------------------------*/ + +/* +** Auxiliary symbol table entry declaration and related +** definitions. +*/ + +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +union external_auxent { + struct { + char x_tagndx[4]; /* str, un, or enum tag indx */ + union { + struct { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + char x_fsize[4]; /* size of function */ + } x_misc; + union { + struct { /* if ISFCN, tag, or .bb */ + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + struct { /* if ISARY, up to 4 dimen. */ + char x_dimen[E_DIMNUM][2]; + } x_ary; + } x_fcnary; + char x_tvndx[2]; /* tv index */ + } x_sym; + + union { + char x_fname[E_FILNMLEN]; + struct { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + } x_file; + + struct { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + } x_scn; + + struct { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ +}; + +#define AUXENT union external_auxent +#define AUXESZ 18 diff --git a/include/coff/h8300.h b/include/coff/h8300.h new file mode 100644 index 00000000000..e14d03db15d --- /dev/null +++ b/include/coff/h8300.h @@ -0,0 +1,201 @@ +/*** coff information for Hitachi H8/300 */ + +/********************** FILE HEADER **********************/ + +struct external_filehdr { + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ +}; + + + +#define H8300MAGIC 0x8300 + + +#define H8300BADMAG(x) (((x).f_magic!=H8300MAGIC)) + +#define FILHDR struct external_filehdr +#define FILHSZ sizeof(FILHDR) + + +/********************** AOUT "OPTIONAL HEADER" **********************/ + + +typedef struct +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ +} +AOUTHDR; + + +#define AOUTHDRSZ (sizeof(AOUTHDR)) +#define AOUTSZ (sizeof(AOUTHDR)) + + + + +/********************** SECTION HEADER **********************/ + + +struct external_scnhdr { + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries*/ + char s_flags[4]; /* flags */ +}; + +/* + * names of "special" sections + */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" + + +#define SCNHDR struct external_scnhdr +#define SCNHSZ sizeof(SCNHDR) + + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + * Line numbers are grouped on a per function basis; first entry in a function + * grouping will have l_lnno = 0 and in place of physical address will be the + * symbol table index of the function name. + */ +struct external_lineno { + union { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } l_addr; + char l_lnno[2]; /* line number */ +}; + + +#define LINENO struct external_lineno +#define LINESZ sizeof(LINENO) + + +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union { + char e_name[E_SYMNMLEN]; + struct { + char e_zeroes[4]; + char e_offset[4]; + } e; + } e; + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; +}; + + + +#define N_BTMASK (017) +#define N_TMASK (060) +#define N_BTSHFT (4) +#define N_TSHIFT (2) + + +union external_auxent { + struct { + char x_tagndx[4]; /* str, un, or enum tag indx */ + union { + struct { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + char x_fsize[4]; /* size of function */ + } x_misc; + union { + struct { /* if ISFCN, tag, or .bb */ + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + struct { /* if ISARY, up to 4 dimen. */ + char x_dimen[E_DIMNUM][2]; + } x_ary; + } x_fcnary; + char x_tvndx[2]; /* tv index */ + } x_sym; + + union { + char x_fname[E_FILNMLEN]; + struct { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + } x_file; + + struct { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + } x_scn; + + struct { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ + + +}; + +#define SYMENT struct external_syment +#define SYMESZ 18 +#define AUXENT union external_auxent +#define AUXESZ 18 + + + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the h8 don't have room in the instruction for the entire + offset - eg the strange jump and high page addressing modes */ + +struct external_reloc { + char r_vaddr[4]; + char r_symndx[4]; + char r_offset[4]; + char r_type[2]; + char r_stuff[2]; +}; + + +#define RELOC struct external_reloc +#define RELSZ 16 + +#define DEFAULT_DATA_SECTION_ALIGNMENT 4 +#define DEFAULT_BSS_SECTION_ALIGNMENT 4 +#define DEFAULT_TEXT_SECTION_ALIGNMENT 4 +/* For new sections we havn't heard of before */ +#define DEFAULT_SECTION_ALIGNMENT 4 diff --git a/include/coff/i386.h b/include/coff/i386.h new file mode 100644 index 00000000000..0683692ff77 --- /dev/null +++ b/include/coff/i386.h @@ -0,0 +1,316 @@ +/*** coff information for M68K */ + + +/********************** FILE HEADER **********************/ + +struct external_filehdr { + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ +}; + + +/* Bits for f_flags: + * F_RELFLG relocation info stripped from file + * F_EXEC file is executable (no unresolved external references) + * F_LNNO line numbers stripped from file + * F_LSYMS local symbols stripped from file + * F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax) + */ + +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +#define F_LSYMS (0x0008) + + + +#define I386MAGIC 0x14c +#define I386BADMAG(x) (((x).f_magic!=I386MAGIC)) + + +#define FILHDR struct external_filehdr +#define FILHSZ sizeof(FILHDR) + + +/********************** AOUT "OPTIONAL HEADER" **********************/ + + +typedef struct +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ +} +AOUTHDR; + +#define AOUTSZ (sizeof(AOUTHDR)) + + +/********************** STORAGE CLASSES **********************/ + +#define C_EFCN -1 /* physical end of function */ +#define C_NULL 0 +#define C_AUTO 1 /* automatic variable */ +#define C_EXT 2 /* external symbol */ +#define C_STAT 3 /* static */ +#define C_REG 4 /* register variable */ +#define C_EXTDEF 5 /* external definition */ +#define C_LABEL 6 /* label */ +#define C_ULABEL 7 /* undefined label */ +#define C_MOS 8 /* member of structure */ +#define C_ARG 9 /* function argument */ +#define C_STRTAG 10 /* structure tag */ +#define C_MOU 11 /* member of union */ +#define C_UNTAG 12 /* union tag */ +#define C_TPDEF 13 /* type definition */ +#define C_USTATIC 14 /* undefined static */ +#define C_ENTAG 15 /* enumeration tag */ +#define C_MOE 16 /* member of enumeration */ +#define C_REGPARM 17 /* register parameter */ +#define C_FIELD 18 /* bit field */ +#define C_AUTOARG 19 /* auto argument */ +#define C_LASTENT 20 /* dummy entry (end of block) */ +#define C_BLOCK 100 /* ".bb" or ".eb" */ +#define C_FCN 101 /* ".bf" or ".ef" */ +#define C_EOS 102 /* end of structure */ +#define C_FILE 103 /* file name */ +#define C_LINE 104 /* line # reformatted as symbol table entry */ +#define C_ALIAS 105 /* duplicate tag */ +#define C_HIDDEN 106 /* ext symbol in dmert public lib */ + +/********************** SECTION HEADER **********************/ + + +struct external_scnhdr { + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries*/ + char s_flags[4]; /* flags */ +}; + +/* + * names of "special" sections + */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _COMMENT ".comment" + +/* + * s_flags "type" + */ +#define STYP_REG (0x0000) /* "regular": allocated, relocated, loaded */ +#define STYP_DSECT (0x0001) /* "dummy": relocated only*/ +#define STYP_NOLOAD (0x0002) /* "noload": allocated, relocated, not loaded */ +#define STYP_GROUP (0x0004) /* "grouped": formed of input sections */ +#define STYP_PAD (0x0008) /* "padding": not allocated, not relocated, loaded */ +#define STYP_COPY (0x0010) /* "copy": for decision function used by field update; not allocated, not relocated, + loaded; reloc & lineno entries processed normally */ +#define STYP_TEXT (0x0020) /* section contains text only */ +#define S_SHRSEG (0x0020) /* In 3b Update files (output of ogen), sections which appear in SHARED segments of the Pfile + will have the S_SHRSEG flag set by ogen, to inform dufr that updating 1 copy of the proc. will + update all process invocations. */ +#define STYP_DATA (0x0040) /* section contains data only */ +#define STYP_BSS (0x0080) /* section contains bss only */ +#define S_NEWFCN (0x0100) /* In a minimal file or an update file, a new function (as compared with a replaced function) */ +#define STYP_INFO (0x0200) /* comment: not allocated not relocated, not loaded */ +#define STYP_OVER (0x0400) /* overlay: relocated not allocated or loaded */ +#define STYP_LIB (0x0800) /* for .lib: same as INFO */ +#define STYP_MERGE (0x2000) /* merge section -- combines with text, data or bss sections only */ +#define STYP_REVERSE_PAD (0x4000) /* section will be padded with no-op instructions wherever padding is necessary and there is a + word of contiguous bytes beginning on a word boundary. */ + +#define SCNHDR struct external_scnhdr +#define SCNHSZ sizeof(SCNHDR) + + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + * Line numbers are grouped on a per function basis; first entry in a function + * grouping will have l_lnno = 0 and in place of physical address will be the + * symbol table index of the function name. + */ +struct external_lineno { + union { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } l_addr; + char l_lnno[2]; /* line number */ +}; + + +#define LINENO struct external_lineno +#define LINESZ 6 + + +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union { + char e_name[E_SYMNMLEN]; + struct { + char e_zeroes[4]; + char e_offset[4]; + } e; + } e; + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; +}; + + +/*#define n_name _n._n_name +#define n_ptr _n._n_nptr[1] +#define n_zeroes _n._n_n._n_zeroes +#define n_offset _n._n_n._n_offset +*/ + +/* + * Relocatable symbols have number of the section in which they are defined, + * or one of the following: + */ +#define N_UNDEF ((short)0) /* undefined symbol */ +#define N_ABS ((short)-1) /* value of symbol is absolute */ +#define N_DEBUG ((short)-2) /* debugging symbol -- value is meaningless */ +#define N_TV ((short)-3) /* indicates symbol needs preload transfer vector */ +#define P_TV ((short)-4) /* indicates symbol needs postload transfer vector*/ + +/* + * Type of a symbol, in low 4 bits of the word + */ +#define T_NULL 0 +#define T_VOID 1 /* function argument (only used by compiler) */ +#define T_CHAR 2 /* character */ +#define T_SHORT 3 /* short integer */ +#define T_INT 4 /* integer */ +#define T_LONG 5 /* long integer */ +#define T_FLOAT 6 /* floating point */ +#define T_DOUBLE 7 /* double word */ +#define T_STRUCT 8 /* structure */ +#define T_UNION 9 /* union */ +#define T_ENUM 10 /* enumeration */ +#define T_MOE 11 /* member of enumeration*/ +#define T_UCHAR 12 /* unsigned character */ +#define T_USHORT 13 /* unsigned short */ +#define T_UINT 14 /* unsigned integer */ +#define T_ULONG 15 /* unsigned long */ +#define T_LNGDBL 16 /* long double */ + +/* + * derived types, in n_type +*/ +#define DT_NON (0) /* no derived type */ +#define DT_PTR (1) /* pointer */ +#define DT_FCN (2) /* function */ +#define DT_ARY (3) /* array */ + +#define N_BTMASK (0xf) +#define N_TMASK (0x30) +#define N_BTSHFT (4) +#define N_TSHIFT (2) + +#define BTYPE(x) ((x) & N_BTMASK) + +#define ISPTR(x) (((x) & N_TMASK) == (DT_PTR << N_BTSHFT)) +#define ISFCN(x) (((x) & N_TMASK) == (DT_FCN << N_BTSHFT)) +#define ISARY(x) (((x) & N_TMASK) == (DT_ARY << N_BTSHFT)) + +#define DECREF(x) ((((x)>>N_TSHIFT)&~N_BTMASK)|((x)&N_BTMASK)) + +union external_auxent { + struct { + char x_tagndx[4]; /* str, un, or enum tag indx */ + union { + struct { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + char x_fsize[4]; /* size of function */ + } x_misc; + union { + struct { /* if ISFCN, tag, or .bb */ + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + struct { /* if ISARY, up to 4 dimen. */ + char x_dimen[E_DIMNUM][2]; + } x_ary; + } x_fcnary; + char x_tvndx[2]; /* tv index */ + } x_sym; + + union { + char x_fname[E_FILNMLEN]; + struct { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + } x_file; + + struct { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + } x_scn; + + struct { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ + + +}; + +#define SYMENT struct external_syment +#define SYMESZ 18 +#define AUXENT union external_auxent +#define AUXESZ 18 + + +# define _ETEXT "etext" + + +/********************** RELOCATION DIRECTIVES **********************/ + + + +struct external_reloc { + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + + +#define RELOC struct external_reloc +#define RELSZ 10 + +#define DEFAULT_DATA_SECTION_ALIGNMENT 4 +#define DEFAULT_BSS_SECTION_ALIGNMENT 4 +#define DEFAULT_TEXT_SECTION_ALIGNMENT 4 +/* For new sections we havn't heard of before */ +#define DEFAULT_SECTION_ALIGNMENT 4 diff --git a/include/opcode/a29k.h b/include/opcode/a29k.h new file mode 100644 index 00000000000..8ed4c461478 --- /dev/null +++ b/include/opcode/a29k.h @@ -0,0 +1,320 @@ +/* Table of opcodes for the AMD 29000 + Copyright (C) 1990, 1991 Free Software Foundation, Inc. + +This file is part of GDB and GAS. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* $Id$ */ + +struct a29k_opcode { + /* Name of the instruction. */ + char *name; + + /* Opcode word */ + unsigned long opcode; + + /* A string of characters which describe the operands. + Valid characters are: + , Itself. The character appears in the assembly code. + a RA. The register number is in bits 8-15 of the instruction. + b RB. The register number is in bits 0-7 of the instruction. + c RC. The register number is in bits 16-23 of the instruction. + i An immediate operand is in bits 0-7 of the instruction. + x Bits 0-7 and 16-23 of the instruction are bits 0-7 and 8-15 + (respectively) of the immediate operand. + h Same as x but the instruction contains bits 16-31 of the + immediate operand. + X Same as x but bits 16-31 of the signed immediate operand + are set to 1 (thus the operand is always negative). + P,A Bits 0-7 and 16-23 of the instruction are bits 2-9 and 10-17 + (respectively) of the immediate operand. + P=PC-relative, sign-extended to 32 bits. + A=Absolute, zero-extended to 32 bits. + e CE bit (bit 23) for a load/store instruction. + n Control field (bits 16-22) for a load/store instruction. + v Immediate operand in bits 16-23 of the instruction. + (used for trap numbers). + s SA. Special-purpose register number in bits 8-15 + of the instruction. + u UI--bit 7 of the instruction. + r RND--bits 4-6 of the instruction. + d FD--bits 2-3 of the instruction. + f FS--bits 0-1 of the instruction. + + Extensions for 29050: + + d FMT--bits 2-3 of the instruction (not really new). + f ACN--bits 0-1 of the instruction (not really new). + F FUNC--Special function in bits 18-21 of the instruction. + C ACN--bits 16-17 specifying the accumlator register. */ + char *args; +}; + +#ifndef CONST +#define CONST +#endif /* CONST */ + +static CONST struct a29k_opcode a29k_opcodes[] = +{ + +{ "add", 0x14000000, "c,a,b" }, +{ "add", 0x15000000, "c,a,i" }, +{ "addc", 0x1c000000, "c,a,b" }, +{ "addc", 0x1d000000, "c,a,i" }, +{ "addcs", 0x18000000, "c,a,b" }, +{ "addcs", 0x19000000, "c,a,i" }, +{ "addcu", 0x1a000000, "c,a,b" }, +{ "addcu", 0x1b000000, "c,a,i" }, +{ "adds", 0x10000000, "c,a,b" }, +{ "adds", 0x11000000, "c,a,i" }, +{ "addu", 0x12000000, "c,a,b" }, +{ "addu", 0x13000000, "c,a,i" }, +{ "and", 0x90000000, "c,a,b" }, +{ "and", 0x91000000, "c,a,i" }, +{ "andn", 0x9c000000, "c,a,b" }, +{ "andn", 0x9d000000, "c,a,i" }, +{ "aseq", 0x70000000, "v,a,b" }, +{ "aseq", 0x71000000, "v,a,i" }, +{ "asge", 0x5c000000, "v,a,b" }, +{ "asge", 0x5d000000, "v,a,i" }, +{ "asgeu", 0x5e000000, "v,a,b" }, +{ "asgeu", 0x5f000000, "v,a,i" }, +{ "asgt", 0x58000000, "v,a,b" }, +{ "asgt", 0x59000000, "v,a,i" }, +{ "asgtu", 0x5a000000, "v,a,b" }, +{ "asgtu", 0x5b000000, "v,a,i" }, +{ "asle", 0x54000000, "v,a,b" }, +{ "asle", 0x55000000, "v,a,i" }, +{ "asleu", 0x56000000, "v,a,b" }, +{ "asleu", 0x57000000, "v,a,i" }, +{ "aslt", 0x50000000, "v,a,b" }, +{ "aslt", 0x51000000, "v,a,i" }, +{ "asltu", 0x52000000, "v,a,b" }, +{ "asltu", 0x53000000, "v,a,i" }, +{ "asneq", 0x72000000, "v,a,b" }, +{ "asneq", 0x73000000, "v,a,i" }, +{ "call", 0xa8000000, "a,P" }, +{ "call", 0xa9000000, "a,A" }, +{ "calli", 0xc8000000, "a,b" }, +{ "class", 0xe6000000, "c,a,f" }, +{ "clz", 0x08000000, "c,b" }, +{ "clz", 0x09000000, "c,i" }, +{ "const", 0x03000000, "a,x" }, +{ "consth", 0x02000000, "a,h" }, +{ "consthz", 0x05000000, "a,h" }, +{ "constn", 0x01000000, "a,X" }, +{ "convert", 0xe4000000, "c,a,u,r,d,f" }, +{ "cpbyte", 0x2e000000, "c,a,b" }, +{ "cpbyte", 0x2f000000, "c,a,i" }, +{ "cpeq", 0x60000000, "c,a,b" }, +{ "cpeq", 0x61000000, "c,a,i" }, +{ "cpge", 0x4c000000, "c,a,b" }, +{ "cpge", 0x4d000000, "c,a,i" }, +{ "cpgeu", 0x4e000000, "c,a,b" }, +{ "cpgeu", 0x4f000000, "c,a,i" }, +{ "cpgt", 0x48000000, "c,a,b" }, +{ "cpgt", 0x49000000, "c,a,i" }, +{ "cpgtu", 0x4a000000, "c,a,b" }, +{ "cpgtu", 0x4b000000, "c,a,i" }, +{ "cple", 0x44000000, "c,a,b" }, +{ "cple", 0x45000000, "c,a,i" }, +{ "cpleu", 0x46000000, "c,a,b" }, +{ "cpleu", 0x47000000, "c,a,i" }, +{ "cplt", 0x40000000, "c,a,b" }, +{ "cplt", 0x41000000, "c,a,i" }, +{ "cpltu", 0x42000000, "c,a,b" }, +{ "cpltu", 0x43000000, "c,a,i" }, +{ "cpneq", 0x62000000, "c,a,b" }, +{ "cpneq", 0x63000000, "c,a,i" }, +{ "dadd", 0xf1000000, "c,a,b" }, +{ "ddiv", 0xf7000000, "c,a,b" }, +{ "deq", 0xeb000000, "c,a,b" }, +{ "dge", 0xef000000, "c,a,b" }, +{ "dgt", 0xed000000, "c,a,b" }, +{ "div", 0x6a000000, "c,a,b" }, +{ "div", 0x6b000000, "c,a,i" }, +{ "div0", 0x68000000, "c,b" }, +{ "div0", 0x69000000, "c,i" }, +{ "divide", 0xe1000000, "c,a,b" }, +{ "dividu", 0xe3000000, "c,a,b" }, +{ "divl", 0x6c000000, "c,a,b" }, +{ "divl", 0x6d000000, "c,a,i" }, +{ "divrem", 0x6e000000, "c,a,b" }, +{ "divrem", 0x6f000000, "c,a,i" }, +{ "dmac", 0xd9000000, "F,C,a,b" }, +{ "dmsm", 0xdb000000, "c,a,b" }, +{ "dmul", 0xf5000000, "c,a,b" }, +{ "dsub", 0xf3000000, "c,a,b" }, +{ "emulate", 0xd7000000, "v,a,b" }, +{ "exbyte", 0x0a000000, "c,a,b" }, +{ "exbyte", 0x0b000000, "c,a,i" }, +{ "exhw", 0x7c000000, "c,a,b" }, +{ "exhw", 0x7d000000, "c,a,i" }, +{ "exhws", 0x7e000000, "c,a" }, +{ "extract", 0x7a000000, "c,a,b" }, +{ "extract", 0x7b000000, "c,a,i" }, +{ "fadd", 0xf0000000, "c,a,b" }, +{ "fdiv", 0xf6000000, "c,a,b" }, +{ "fdmul", 0xf9000000, "c,a,b" }, +{ "feq", 0xea000000, "c,a,b" }, +{ "fge", 0xee000000, "c,a,b" }, +{ "fgt", 0xec000000, "c,a,b" }, +{ "fmac", 0xd8000000, "F,C,a,b" }, +{ "fmsm", 0xda000000, "c,a,b" }, +{ "fmul", 0xf4000000, "c,a,b" }, +{ "fsub", 0xf2000000, "c,a,b" }, +{ "halt", 0x89000000, "" }, +{ "inbyte", 0x0c000000, "c,a,b" }, +{ "inbyte", 0x0d000000, "c,a,i" }, +{ "inhw", 0x78000000, "c,a,b" }, +{ "inhw", 0x79000000, "c,a,i" }, +{ "inv", 0x9f000000, "" }, +{ "iret", 0x88000000, "" }, +{ "iretinv", 0x8c000000, "" }, +{ "jmp", 0xa0000000, "P" }, +{ "jmp", 0xa1000000, "A" }, +{ "jmpf", 0xa4000000, "a,P" }, +{ "jmpf", 0xa5000000, "a,A" }, +{ "jmpfdec", 0xb4000000, "a,P" }, +{ "jmpfdec", 0xb5000000, "a,A" }, +{ "jmpfi", 0xc4000000, "a,b" }, +{ "jmpi", 0xc0000000, "b" }, +{ "jmpt", 0xac000000, "a,P" }, +{ "jmpt", 0xad000000, "a,A" }, +{ "jmpti", 0xcc000000, "a,b" }, +{ "load", 0x16000000, "e,n,a,b" }, +{ "load", 0x17000000, "e,n,a,i" }, +{ "loadl", 0x06000000, "e,n,a,b" }, +{ "loadl", 0x07000000, "e,n,a,i" }, +{ "loadm", 0x36000000, "e,n,a,b" }, +{ "loadm", 0x37000000, "e,n,a,i" }, +{ "loadset", 0x26000000, "e,n,a,b" }, +{ "loadset", 0x27000000, "e,n,a,i" }, +{ "mfacc", 0xe9000100, "c,d,f" }, +{ "mfsr", 0xc6000000, "c,s" }, +{ "mftlb", 0xb6000000, "c,a" }, +{ "mtacc", 0xe8010000, "a,d,f" }, +{ "mtsr", 0xce000000, "s,b" }, +{ "mtsrim", 0x04000000, "s,x" }, +{ "mttlb", 0xbe000000, "a,b" }, +{ "mul", 0x64000000, "c,a,b" }, +{ "mul", 0x65000000, "c,a,i" }, +{ "mull", 0x66000000, "c,a,b" }, +{ "mull", 0x67000000, "c,a,i" }, +{ "multiplu", 0xe2000000, "c,a,b" }, +{ "multiply", 0xe0000000, "c,a,b" }, +{ "multm", 0xde000000, "c,a,b" }, +{ "multmu", 0xdf000000, "c,a,b" }, +{ "mulu", 0x74000000, "c,a,b" }, +{ "mulu", 0x75000000, "c,a,i" }, +{ "nand", 0x9a000000, "c,a,b" }, +{ "nand", 0x9b000000, "c,a,i" }, +{ "nop", 0x70400101, "" }, +{ "nor", 0x98000000, "c,a,b" }, +{ "nor", 0x99000000, "c,a,i" }, +{ "or", 0x92000000, "c,a,b" }, +{ "or", 0x93000000, "c,a,i" }, +{ "orn", 0xaa000000, "c,a,b" }, +{ "orn", 0xab000000, "c,a,i" }, + +/* The description of "setip" in Chapter 8 ("instruction set") of the user's + manual claims that these are absolute register numbers. But section + 7.2.1 explains that they are not. The latter is correct, so print + these normally ("lr0", "lr5", etc.). */ +{ "setip", 0x9e000000, "c,a,b" }, + +{ "sll", 0x80000000, "c,a,b" }, +{ "sll", 0x81000000, "c,a,i" }, +{ "sqrt", 0xe5000000, "c,a,f" }, +{ "sra", 0x86000000, "c,a,b" }, +{ "sra", 0x87000000, "c,a,i" }, +{ "srl", 0x82000000, "c,a,b" }, +{ "srl", 0x83000000, "c,a,i" }, +{ "store", 0x1e000000, "e,n,a,b" }, +{ "store", 0x1f000000, "e,n,a,i" }, +{ "storel", 0x0e000000, "e,n,a,b" }, +{ "storel", 0x0f000000, "e,n,a,i" }, +{ "storem", 0x3e000000, "e,n,a,b" }, +{ "storem", 0x3f000000, "e,n,a,i" }, +{ "sub", 0x24000000, "c,a,b" }, +{ "sub", 0x25000000, "c,a,i" }, +{ "subc", 0x2c000000, "c,a,b" }, +{ "subc", 0x2d000000, "c,a,i" }, +{ "subcs", 0x28000000, "c,a,b" }, +{ "subcs", 0x29000000, "c,a,i" }, +{ "subcu", 0x2a000000, "c,a,b" }, +{ "subcu", 0x2b000000, "c,a,i" }, +{ "subr", 0x34000000, "c,a,b" }, +{ "subr", 0x35000000, "c,a,i" }, +{ "subrc", 0x3c000000, "c,a,b" }, +{ "subrc", 0x3d000000, "c,a,i" }, +{ "subrcs", 0x38000000, "c,a,b" }, +{ "subrcs", 0x39000000, "c,a,i" }, +{ "subrcu", 0x3a000000, "c,a,b" }, +{ "subrcu", 0x3b000000, "c,a,i" }, +{ "subrs", 0x30000000, "c,a,b" }, +{ "subrs", 0x31000000, "c,a,i" }, +{ "subru", 0x32000000, "c,a,b" }, +{ "subru", 0x33000000, "c,a,i" }, +{ "subs", 0x20000000, "c,a,b" }, +{ "subs", 0x21000000, "c,a,i" }, +{ "subu", 0x22000000, "c,a,b" }, +{ "subu", 0x23000000, "c,a,i" }, +{ "xnor", 0x96000000, "c,a,b" }, +{ "xnor", 0x97000000, "c,a,i" }, +{ "xor", 0x94000000, "c,a,b" }, +{ "xor", 0x95000000, "c,a,i" }, + +{ "", 0x0, "" } /* Dummy entry, not included in NUM_OPCODES. This + lets code examine entry i+1 without checking + if we've run off the end of the table. */ +}; + +CONST unsigned int num_opcodes = (((sizeof a29k_opcodes) / (sizeof a29k_opcodes[0])) - 1); + +/* + * $Log$ + * Revision 1.1 1991/12/01 02:22:19 sac + * Initial revision + * + * Revision 1.5 1991/11/07 16:59:19 sac + * Fixed encoding of mtacc instruction. + * + * Revision 1.4 1991/08/06 07:20:27 rich + * Fixing CONST declarations. + * + * Revision 1.3 1991/08/05 22:31:05 rich + * *** empty log message *** + * + * Revision 1.2 1991/07/15 23:34:04 steve + * *** empty log message *** + * + * Revision 1.1 1991/05/19 00:19:33 rich + * Initial revision + * + * Revision 1.1.1.1 1991/04/04 18:15:23 rich + * new gas main line + * + * Revision 1.1 1991/04/04 18:15:23 rich + * Initial revision + * + * Revision 1.2 1991/03/30 17:13:19 rich + * num_opcodes now unsigned. Also, added rcsid and log. + * + * + */ + +/* end of a29k-opcode.h */ diff --git a/include/opcode/arm.h b/include/opcode/arm.h new file mode 100644 index 00000000000..d968e6ef8fd --- /dev/null +++ b/include/opcode/arm.h @@ -0,0 +1,294 @@ +/* ARM opcode list. + Copyright (C) 1989, Free Software Foundation, Inc. + +This file is part of GDB and GAS. + +GDB and GAS are free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GDB and GAS are distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GDB or GAS; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* types of instruction (encoded in bits 26 and 27 of the instruction) */ + +#define TYPE_ARITHMETIC 0 +#define TYPE_LDR_STR 1 +#define TYPE_BLOCK_BRANCH 2 +#define TYPE_SWI 3 + +/* bit 25 decides whether an instruction is a block move or a branch */ +#define SUBTYPE_BLOCK 0 +#define SUBTYPE_BRANCH 1 + +/* codes to distinguish the arithmetic instructions */ + +#define OPCODE_AND 0 +#define OPCODE_EOR 1 +#define OPCODE_SUB 2 +#define OPCODE_RSB 3 +#define OPCODE_ADD 4 +#define OPCODE_ADC 5 +#define OPCODE_SBC 6 +#define OPCODE_RSC 7 +#define OPCODE_TST 8 +#define OPCODE_TEQ 9 +#define OPCODE_CMP 10 +#define OPCODE_CMN 11 +#define OPCODE_ORR 12 +#define OPCODE_MOV 13 +#define OPCODE_BIC 14 +#define OPCODE_MVN 15 + +/* condition codes */ + +#define COND_EQ 0 +#define COND_NE 1 +#define COND_CS 2 +#define COND_CC 3 +#define COND_MI 4 +#define COND_PL 5 +#define COND_VS 6 +#define COND_VC 7 +#define COND_HI 8 +#define COND_LS 9 +#define COND_GE 10 +#define COND_LT 11 +#define COND_GT 12 +#define COND_LE 13 +#define COND_AL 14 +#define COND_NV 15 + +/* Describes the format of an ARM machine instruction */ + +struct generic_fmt { + unsigned rest :25; /* the rest of the instruction */ + unsigned subtype :1; /* used to decide between block and branch */ + unsigned type :2; /* one of TYPE_* */ + unsigned cond :4; /* one of COND_* defined above */ +}; + +struct arith_fmt { + unsigned operand2 :12; /* #nn or rn or rn shift #m or rn shift rm */ + unsigned dest :4; /* place where the answer goes */ + unsigned operand1 :4; /* first operand to instruction */ + unsigned set :1; /* == 1 means set processor flags */ + unsigned opcode :4; /* one of OPCODE_* defined above */ + unsigned immed :1; /* operand2 is an immediate value */ + unsigned type :2; /* == TYPE_ARITHMETIC */ + unsigned cond :4; /* one of COND_* defined above */ +}; + +struct ldr_str_fmt { + unsigned offset :12; /* #nn or rn or rn shift #m */ + unsigned reg :4; /* destination for LDR, source for STR */ + unsigned base :4; /* base register */ + unsigned is_load :1; /* == 1 for LDR */ + unsigned writeback :1; /* == 1 means write back (base+offset) into base */ + unsigned byte :1; /* == 1 means byte access else word */ + unsigned up :1; /* == 1 means add offset else subtract it */ + unsigned pre_index :1; /* == 1 means [a,b] form else [a],b form */ + unsigned immed :1; /* == 0 means immediate offset */ + unsigned type :2; /* == TYPE_LDR_STR */ + unsigned cond :4; /* one of COND_* defined above */ +}; + +struct block_fmt { + unsigned mask :16; /* register mask */ + unsigned base :4; /* register used as base of move */ + unsigned is_load :1; /* == 1 for LDM */ + unsigned writeback :1; /* == 1 means update base after move */ + unsigned set :1; /* == 1 means set flags in pc if included in mask */ + unsigned increment :1; /* == 1 means increment base register */ + unsigned before :1; /* == 1 means inc/dec before each move */ + unsigned is_block :1; /* == SUBTYPE_BLOCK */ + unsigned type :2; /* == TYPE_BLOCK_BRANCH */ + unsigned cond :4; /* one of COND_* defined above */ +}; + +struct branch_fmt { + unsigned dest :24; /* destination of the branch */ + unsigned link :1; /* branch with link (function call) */ + unsigned is_branch :1; /* == SUBTYPE_BRANCH */ + unsigned type :2; /* == TYPE_BLOCK_BRANCH */ + unsigned cond :4; /* one of COND_* defined above */ +}; + +#define ROUND_N 0 +#define ROUND_P 1 +#define ROUND_M 2 +#define ROUND_Z 3 + +#define FLOAT2_MVF 0 +#define FLOAT2_MNF 1 +#define FLOAT2_ABS 2 +#define FLOAT2_RND 3 +#define FLOAT2_SQT 4 +#define FLOAT2_LOG 5 +#define FLOAT2_LGN 6 +#define FLOAT2_EXP 7 +#define FLOAT2_SIN 8 +#define FLOAT2_COS 9 +#define FLOAT2_TAN 10 +#define FLOAT2_ASN 11 +#define FLOAT2_ACS 12 +#define FLOAT2_ATN 13 + +#define FLOAT3_ADF 0 +#define FLOAT3_MUF 1 +#define FLOAT3_SUF 2 +#define FLOAT3_RSF 3 +#define FLOAT3_DVF 4 +#define FLOAT3_RDF 5 +#define FLOAT3_POW 6 +#define FLOAT3_RPW 7 +#define FLOAT3_RMF 8 +#define FLOAT3_FML 9 +#define FLOAT3_FDV 10 +#define FLOAT3_FRD 11 +#define FLOAT3_POL 12 + +struct float2_fmt { + unsigned operand2 :3; /* second operand */ + unsigned immed :1; /* == 1 if second operand is a constant */ + unsigned pad1 :1; /* == 0 */ + unsigned rounding :2; /* ROUND_* */ + unsigned is_double :1; /* == 1 if precision is double (only if not extended) */ + unsigned pad2 :4; /* == 1 */ + unsigned dest :3; /* destination */ + unsigned is_2_op :1; /* == 1 if 2 operand ins */ + unsigned operand1 :3; /* first operand (only of is_2_op == 0) */ + unsigned is_extended :1; /* == 1 if precision is extended */ + unsigned opcode :4; /* FLOAT2_* or FLOAT3_* depending on is_2_op */ + unsigned must_be_2 :2; /* == 2 */ + unsigned type :2; /* == TYPE_SWI */ + unsigned cond :4; /* COND_* */ +}; + +struct swi_fmt { + unsigned argument :24; /* argument to SWI (syscall number) */ + unsigned must_be_3 :2; /* == 3 */ + unsigned type :2; /* == TYPE_SWI */ + unsigned cond :4; /* one of COND_* defined above */ +}; + +union insn_fmt { + struct generic_fmt generic; + struct arith_fmt arith; + struct ldr_str_fmt ldr_str; + struct block_fmt block; + struct branch_fmt branch; + struct swi_fmt swi; + unsigned long ins; +}; + +struct opcode { + unsigned long value, mask; /* recognise instruction if (op&mask)==value */ + char *assembler; /* how to disassemble this instruction */ +}; + +/* format of the assembler string : + + %% % + %d print the bitfield in decimal + %x print the bitfield in hex + %r print as an ARM register + %f print a floating point constant if >7 else an fp register + %c print condition code (always bits 28-31) + %P print floating point precision in arithmetic insn + %Q print floating point precision in ldf/stf insn + %R print floating point rounding mode + %'c print specified char iff bit is one + %`c print specified char iff bit is zero + %?ab print a if bit is one else print b + %p print 'p' iff bits 12-15 are 15 + %o print operand2 (immediate or register + shift) + %a print address for ldr/str instruction + %b print branch destination + %A print address for ldc/stc/ldf/stf instruction + %m print register mask for ldm/stm instruction +*/ + +static struct opcode opcodes[] = { + /* ARM instructions */ + 0x00000090, 0x0fe000f0, "mul%20's %12-15r, %16-19r, %0-3r", + 0x00200090, 0x0fe000f0, "mla%20's %12-15r, %16-19r, %0-3r, %8-11r", + 0x00000000, 0x0de00000, "and%c%20's %12-15r, %16-19r, %o", + 0x00200000, 0x0de00000, "eor%c%20's %12-15r, %16-19r, %o", + 0x00400000, 0x0de00000, "sub%c%20's %12-15r, %16-19r, %o", + 0x00600000, 0x0de00000, "rsb%c%20's %12-15r, %16-19r, %o", + 0x00800000, 0x0de00000, "add%c%20's %12-15r, %16-19r, %o", + 0x00a00000, 0x0de00000, "adc%c%20's %12-15r, %16-19r, %o", + 0x00c00000, 0x0de00000, "sbc%c%20's %12-15r, %16-19r, %o", + 0x00e00000, 0x0de00000, "rsc%c%20's %12-15r, %16-19r, %o", + 0x01000000, 0x0de00000, "tst%c%p %16-19r, %o", + 0x01200000, 0x0de00000, "teq%c%p %16-19r, %o", + 0x01400000, 0x0de00000, "cmp%c%p %16-19r, %o", + 0x01600000, 0x0de00000, "cmn%c%p %16-19r, %o", + 0x01800000, 0x0de00000, "orr%c%20's %12-15r, %16-19r, %o", + 0x01a00000, 0x0de00000, "mov%c%20's %12-15r, %o", + 0x01c00000, 0x0de00000, "bic%c%20's %12-15r, %16-19r, %o", + 0x01e00000, 0x0de00000, "mvn%c%20's %12-15r, %o", + 0x04000000, 0x0c100000, "str%c%22'b %12-15r, %a", + 0x04100000, 0x0c100000, "ldr%c%22'b %12-15r, %a", + 0x08000000, 0x0e100000, "stm%c%23?id%24?ba %16-19r%22`!, %m", + 0x08100000, 0x0e100000, "ldm%c%23?id%24?ba %16-19r%22`!, %m%22'^", + 0x0a000000, 0x0e000000, "b%c%24'l %b", + 0x0f000000, 0x0f000000, "swi%c %0-23x", + /* Floating point coprocessor instructions */ + 0x0e000100, 0x0ff08f10, "adf%c%P%R %12-14f, %16-18f, %0-3f", + 0x0e100100, 0x0ff08f10, "muf%c%P%R %12-14f, %16-18f, %0-3f", + 0x0e200100, 0x0ff08f10, "suf%c%P%R %12-14f, %16-18f, %0-3f", + 0x0e300100, 0x0ff08f10, "rsf%c%P%R %12-14f, %16-18f, %0-3f", + 0x0e400100, 0x0ff08f10, "dvf%c%P%R %12-14f, %16-18f, %0-3f", + 0x0e500100, 0x0ff08f10, "rdf%c%P%R %12-14f, %16-18f, %0-3f", + 0x0e600100, 0x0ff08f10, "pow%c%P%R %12-14f, %16-18f, %0-3f", + 0x0e700100, 0x0ff08f10, "rpw%c%P%R %12-14f, %16-18f, %0-3f", + 0x0e800100, 0x0ff08f10, "rmf%c%P%R %12-14f, %16-18f, %0-3f", + 0x0e900100, 0x0ff08f10, "fml%c%P%R %12-14f, %16-18f, %0-3f", + 0x0ea00100, 0x0ff08f10, "fdv%c%P%R %12-14f, %16-18f, %0-3f", + 0x0eb00100, 0x0ff08f10, "frd%c%P%R %12-14f, %16-18f, %0-3f", + 0x0ec00100, 0x0ff08f10, "pol%c%P%R %12-14f, %16-18f, %0-3f", + 0x0e008100, 0x0ff08f10, "mvf%c%P%R %12-14f, %0-3f", + 0x0e108100, 0x0ff08f10, "mnf%c%P%R %12-14f, %0-3f", + 0x0e208100, 0x0ff08f10, "abs%c%P%R %12-14f, %0-3f", + 0x0e308100, 0x0ff08f10, "rnd%c%P%R %12-14f, %0-3f", + 0x0e408100, 0x0ff08f10, "sqt%c%P%R %12-14f, %0-3f", + 0x0e508100, 0x0ff08f10, "log%c%P%R %12-14f, %0-3f", + 0x0e608100, 0x0ff08f10, "lgn%c%P%R %12-14f, %0-3f", + 0x0e708100, 0x0ff08f10, "exp%c%P%R %12-14f, %0-3f", + 0x0e808100, 0x0ff08f10, "sin%c%P%R %12-14f, %0-3f", + 0x0e908100, 0x0ff08f10, "cos%c%P%R %12-14f, %0-3f", + 0x0ea08100, 0x0ff08f10, "tan%c%P%R %12-14f, %0-3f", + 0x0eb08100, 0x0ff08f10, "asn%c%P%R %12-14f, %0-3f", + 0x0ec08100, 0x0ff08f10, "acs%c%P%R %12-14f, %0-3f", + 0x0ed08100, 0x0ff08f10, "atn%c%P%R %12-14f, %0-3f", + 0x0e000110, 0x0ff00f1f, "flt%c%P%R %16-18f, %12-15r", + 0x0e100110, 0x0fff0f98, "fix%c%R %12-15r, %0-2f", + 0x0e200110, 0x0fff0fff, "wfs%c %12-15r", + 0x0e300110, 0x0fff0fff, "rfs%c %12-15r", + 0x0e400110, 0x0fff0fff, "wfc%c %12-15r", + 0x0e500110, 0x0fff0fff, "rfc%c %12-15r", + 0x0e90f110, 0x0ff8fff0, "cmf%c %16-18f, %0-3f", + 0x0eb0f110, 0x0ff8fff0, "cnf%c %16-18f, %0-3f", + 0x0ed0f110, 0x0ff8fff0, "cmfe%c %16-18f, %0-3f", + 0x0ef0f110, 0x0ff8fff0, "cnfe%c %16-18f, %0-3f", + 0x0c000100, 0x0e100f00, "stf%c%Q %12-14f, %A", + 0x0c100100, 0x0e100f00, "ldf%c%Q %12-14f, %A", + /* Generic coprocessor instructions */ + 0x0e000000, 0x0f000010, "cdp%c %8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}", + 0x0e000010, 0x0f100010, "mrc%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}", + 0x0e100010, 0x0f100010, "mcr%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}", + 0x0c000000, 0x0e100000, "stc%c%22`l %8-11d, cr%12-15d, %A", + 0x0c100000, 0x0e100000, "ldc%c%22`l %8-11d, cr%12-15d, %A", + /* the rest */ + 0x00000000, 0x00000000, "undefined instruction %0-31x", +}; +#define N_OPCODES (sizeof opcodes / sizeof opcodes[0]) diff --git a/include/opcode/h8300.h b/include/opcode/h8300.h new file mode 100644 index 00000000000..92da20630d5 --- /dev/null +++ b/include/opcode/h8300.h @@ -0,0 +1,233 @@ +/* Opcode table for the H8-300 + Copyright (C) 1989, 1991 Free Software Foundation. + Written by Steve Chamberlain, steve@cygnus.com. + +This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +typedef enum op_type + { +Hex0=0, +Hex1,Hex2,Hex3,Hex4,Hex5,Hex6,Hex7,Hex8,Hex9,HexA,HexB,HexC,HexD,HexE,HexF, + START = 0x20, + KBIT, /* K is #1, or #2, yielding 0x0 or 0x8 */ + IMM3, /* bit number */ + RD8, /* 8 bit reg as 2nd op */ + RD16, /* 16 bit reg as 2nd op */ + RS8, /* 8 bit reg as 1st op */ + RS16, /* 16 bit reg 1st op */ + IMM8, /* constant which fits into 8 bits */ + IMM16, /* constant which fits into 16 bits */ + CCR, /* CCR reg */ + ABS8SRC, /* abs 8 address mode */ + ABS8DST, /* abs 8 address mode */ + DISP8, /* pc rel displacement */ + ABS16SRC, /* abs 16 address mode */ + ABS16DST, /* abs 16 address mode */ + DISPSRC, /* @(r:16) address mode src */ + DISPDST, /* @(r:16) address mode dst*/ + DISPREG, /* register from DISP address mode */ + RDDEC, /* @-rn mode */ + RSINC, /* @rn+ mode */ + RDIND, /* @R mode dst */ + RSIND, /* @R mode src */ + MEMIND, /* @@r8 mode */ + IGNORE, + B30 = 0x40, /* bit 3 must be low */ + B31 = 0x80, /* bit 3 must be high */ + + E /* End of list */ + } op_type; + + +struct code { + + op_type nib[9]; +} ; + +struct h8_opcode { + int length; + int noperands; /* Number of operands this opcode takes */ + int nopcodes; /* Number of opcodes with same mnemonic */ + char *name; + struct code args; + struct code data; +int value; +}; + + + +struct h8_opcode h8_opcodes[] +#ifdef DEFINE_TABLE + +#define BITOP(n,imm, name, op00, op01,op10,op11, op20,op21)\ +{ 2, 2,n, name, {imm,RD8,E}, {op00, op01, imm, RD8,E}},\ +{ 4, 2,n, name, {imm,RDIND,E}, {op10, op11, RDIND, 0, op00,op01, imm, 0,E}},\ +{ 4, 2,n, name, {imm,ABS8DST,E}, {op20, op21, ABS8DST, IGNORE, op00,op01, imm, 0,E}} + +#define EBITOP(n,imm, name, op00, op01,op10,op11, op20,op21)\ + BITOP(n,imm, name, op00+1, op01, op10,op11, op20,op21),\ + BITOP(n, RS8, name, op00, op01, op10,op11, op20,op21) + +#define BRANCH(name, op) \ +{ 2, 1, 1,name,{DISP8,E}, { Hex4, op, DISP8,IGNORE,E }} + +#define TWOOP(name, op1, op2,op3) \ +{ 2, 2, 2, name, {IMM8, RD8,E}, { op1, RD8, IMM8,IGNORE,E}},\ +{ 2, 2, 2, name, {RS8, RD8, E}, { op2, op3, RS8, RD8 ,E}} + +#define UNOP(name, op1, op2) \ +{ 2, 1, 1, name, {RS8, E}, { op1, op2, 0, RS8, E}} + +#define UNOP3(name, op1, op2, op3) \ +{2, 1, 1, name , {RS8, E}, {op1, op2, op3, RS8, E}} + +#define WTWOP(name, op1, op2) \ +{2, 2, 1, name, {RS16, RD16, E}, { op1, op2, RS16, RD16, E}} + += +{ + TWOOP("add.b", Hex8, Hex0,Hex8), + WTWOP("add.w", Hex0, Hex9), + { 2, 2, 1, "adds", {KBIT,RD16|B30, E},{Hex0, HexB, KBIT, RD16|B30, E}}, + TWOOP("addx", Hex9,Hex0,HexE), + TWOOP("and", HexE,Hex1,Hex6), + { 2, 2, 1, "andc", {IMM8, CCR, E}, { Hex0, Hex6, IMM8,IGNORE, E}}, + BITOP(3,IMM3|B30, "band", Hex7, Hex6, Hex7, HexC, Hex7, HexE), + BRANCH("bra", Hex0), + BRANCH("bt", Hex0), + BRANCH("brn", Hex1), + BRANCH("bf", Hex1), + BRANCH("bhi", Hex2), + BRANCH("bls", Hex3), + BRANCH("bcc", Hex4), + BRANCH("bhs", Hex4), + BRANCH("bcs", Hex5), + BRANCH("blo", Hex5), + BRANCH("bne", Hex6), + BRANCH("beq", Hex7), + BRANCH("bvc", Hex8), + BRANCH("bvs", Hex9), + BRANCH("bpl", HexA), + BRANCH("bmi", HexB), + BRANCH("bge", HexC), + BRANCH("blt", HexD), + BRANCH("bgt", HexE), + BRANCH("ble", HexF), + EBITOP(6,IMM3|B30,"bclr", Hex6, Hex2, Hex7, HexD, Hex7, HexF), + BITOP(3,IMM3|B31,"biand", Hex7, Hex6, Hex7, HexC, Hex7, HexE), + BITOP(3,IMM3|B31, "bild", Hex7, Hex7,Hex7, HexC, Hex7, HexE), + BITOP(3,IMM3|B31, "bior", Hex7, Hex4,Hex7, HexC, Hex7, HexE), + BITOP(3,IMM3|B31, "bist", Hex6, Hex7,Hex7, HexD, Hex7, HexE), + BITOP(3,IMM3|B31, "bixor", Hex7, Hex5,Hex7, HexC, Hex7, HexE), + BITOP(3,IMM3|B30, "bld", Hex7, Hex7,Hex7, HexC, Hex7, HexE), + EBITOP(6,IMM3|B30,"bnot", Hex6, Hex1, Hex7, HexD, Hex7, HexF), + BITOP(3,IMM3|B30,"bor", Hex7, Hex4,Hex7, HexC, Hex7, HexE), + EBITOP(6,IMM3|B30,"bset", Hex6, Hex0,Hex7, HexD, Hex7, HexF), + { 2, 1, 1, "bsr",{DISP8, E},{ Hex5, Hex5, DISP8,IGNORE, E}}, + BITOP(3,IMM3|B30, "bst", Hex6, Hex7,Hex7, HexD, Hex7, HexF), + EBITOP(6,IMM3|B30, "btst", Hex6, Hex3,Hex7, HexC, Hex7, HexE), + BITOP(3,IMM3|B30, "bxor", Hex7,Hex5,Hex7, HexC, Hex7, HexE), + TWOOP( "cmp.b",HexA, Hex1, HexC), + WTWOP( "cmp.w",Hex1,HexD), + UNOP( "daa",Hex0, HexF), + UNOP( "das",Hex1, HexF), + UNOP( "dec",Hex1, HexA), + { 2, 2, 1, "divxu",{RS8, RD16|B30, E}, { Hex5, Hex1, RS8, RD16|B30, E}}, + { 4, 0, 1, "eepmov",{ E}, {Hex7, HexB, Hex5, HexC, Hex5, Hex9, Hex8, HexF,E}}, + UNOP( "inc", Hex0, HexA), + { 2, 1, 3, "jmp",{RSIND|B30, E}, {Hex5, Hex9, RSIND|B30, Hex0, E}}, + { 4, 1, 3, "jmp",{ABS16SRC, E}, {Hex5, HexA, Hex0, Hex0, ABS16SRC, IGNORE,IGNORE,IGNORE,E}}, + { 2, 1, 3, "jmp",{MEMIND, E}, {Hex5, HexB, MEMIND,IGNORE, E}}, + { 2, 1, 3, "jsr",{RSIND|B30, E}, {Hex5, HexD, RSIND|B30, Hex0, E}}, + { 4, 1, 3, "jsr",{ABS16SRC, E}, {Hex5, HexE, Hex0, Hex0, ABS16SRC,IGNORE,IGNORE,IGNORE, E}}, + { 2, 1, 3, "jsr",{MEMIND, E}, {Hex5, HexF, MEMIND, IGNORE,E}}, + { 2, 2, 2, "ldc", {IMM8, CCR, E}, { Hex0, Hex7, IMM8,IGNORE, E}}, + { 2, 2, 2, "ldc", {RS8, CCR, E}, { Hex0, Hex3, Hex0, RS8, E}}, + + { 2, 2,13, "mov.b", {RS8, RD8, E}, { Hex0, HexC, RS8, RD8, E}}, + { 2, 2,13, "mov.b", {IMM8, RD8, E}, { HexF, RD8, IMM8,IGNORE, E}}, + { 2, 2,13, "mov.b", {RSIND|B30,RD8, E}, { Hex6, Hex8, RSIND|B30, RD8, E}}, + { 4, 2,13, "mov.b", {DISPSRC,RD8, E}, { Hex6, HexE, DISPREG|B30, RD8, DISPSRC, IGNORE, IGNORE, IGNORE, E}} , + { 2, 2,13, "mov.b", {RSINC|B30, RD8, E}, { Hex6, HexC, RSINC|B30, RD8, E}}, + + { 4, 2,13, "mov.b", {ABS16SRC, RD8, E}, { Hex6, HexA, Hex0, RD8,ABS16SRC, IGNORE,IGNORE,IGNORE,E}}, + { 2, 2,13, "mov.b", {ABS8SRC, RD8, E}, { Hex2, RD8, ABS8SRC,IGNORE, E}}, + { 2, 2,13, "mov.b", {RS8, RDIND|B30, E}, { Hex6, Hex8, RDIND|B31, RS8, E}}, + { 4, 2,13, "mov.b", {RS8, DISPDST, E}, { Hex6, HexE, DISPREG|B31, RS8,DISPDST, IGNORE, IGNORE, IGNORE, E}}, + { 2, 2,13, "mov.b", {RS8, RDDEC|B31, E}, { Hex6, HexC, RDDEC|B31, RS8, E}}, +/* Put the 16 bit one in first so it matches first */ + { 4, 2,13, "mov.b", {RS8, ABS16DST, E}, { Hex6, HexA, Hex8, RS8, ABS16DST,IGNORE,IGNORE,IGNORE, E}}, + { 2, 2,13, "mov.b", {RS8, ABS8DST, E}, { Hex3, RS8, ABS8DST,IGNORE, E}}, + { 2, 2,11, "mov.w", {RS16|B30, RD16|B30, E},{ Hex0, HexD, RS16|B30, RD16|B30, E}}, + { 4, 2,11, "mov.w", {IMM16, RD16|B30, E}, { Hex7, Hex9, Hex0, RD16|B30, IMM16,IGNORE,IGNORE,IGNORE, E}}, + { 2, 2,11, "mov.w", {RSIND|B30,RD16|B30, E},{ Hex6, Hex9, RSIND|B30, RD16|B30, E}}, + { 4, 2,11, "mov.w", {DISPSRC,RD16|B30, E}, { Hex6, HexF, DISPREG|B30, RD16|B30, DISPSRC, IGNORE, IGNORE, IGNORE,E}} , + { 2, 2,11, "mov.w", {RSINC|B30, RD16|B30, E}, { Hex6, HexD, RSINC|B30, RD16|B30, E}}, + { 4, 2,11, "mov.w", {ABS16SRC, RD16|B30, E}, { Hex6, HexB, Hex0, RD16|B30,ABS16SRC,IGNORE,IGNORE,IGNORE, E}}, + { 2, 2,11, "mov.w", {RS16|B30, RDIND|B30, E},{ Hex6, Hex9, RDIND|B31, RS16|B30, E}}, + { 4, 2,11, "mov.w", {RS16|B30, DISPDST, E}, { Hex6, HexF, DISPREG|B31, RS16|B30,DISPDST, IGNORE,IGNORE,IGNORE,E}}, + { 2, 2,11, "mov.w", {RS16|B30, RDDEC|B30, E},{ Hex6, HexD, RDDEC|B31, RS16|B30, E}}, + { 4, 2,11, "mov.w", {RS16|B30, ABS16DST, E}, { Hex6, HexB, Hex8, RS16|B30, ABS16DST, IGNORE, IGNORE, IGNORE, E}}, + + + { 4, 2,1, "movfpe", {ABS16SRC, RD8, E}, { Hex6, HexA, Hex4, RD8, ABS16SRC,IGNORE,IGNORE,IGNORE, E}}, + { 4, 2,1, "movtpe", {RS8, ABS16DST, E}, { Hex6, HexA, HexC, RS8, ABS16DST,IGNORE,IGNORE,IGNORE, E}}, + { 2, 2,1, "mulxu", {RS8, RD16|B30, E}, { Hex5, Hex0, RS8, RD16|B30, E}}, + { 2, 1,1, "neg", {RS8, E}, { Hex1, Hex7, Hex8, RS8, E}}, + { 2, 0,1, "nop", {E}, { Hex0, Hex0, Hex0, Hex0,E}}, + { 2, 1,1, "not", {RS8,E}, { Hex1, Hex7, Hex0, RS8,E}}, + TWOOP("or", HexC, Hex1, Hex4), + { 2, 2,1, "orc", {IMM8, CCR,E}, { Hex0, Hex4, IMM8,IGNORE,E}}, + { 2, 1,1, "pop", {RS16|B30,E}, { Hex6, HexD, Hex7, RS16|B30,E}}, + { 2, 1,1, "push", {RS16|B30,E}, { Hex6, HexD, HexF, RS16|B30,E}}, + UNOP3( "rotl",Hex1, Hex2,Hex8), + UNOP3( "rotr",Hex1, Hex3, Hex8), + UNOP3( "rotxl",Hex1, Hex2, Hex0), + UNOP3( "rotxr",Hex1, Hex3, Hex0), + { 2, 0, 1, "rte", {E}, { Hex5, Hex6, Hex7, Hex0,E}}, + { 2, 0, 1, "rts", {E}, { Hex5, Hex4, Hex7, Hex0,E}}, + UNOP3( "shal", Hex1, Hex0, Hex8), + UNOP3( "shar", Hex1, Hex1, Hex8), + UNOP3( "shll", Hex1, Hex0, Hex0), + UNOP3( "shlr", Hex1, Hex1, Hex0), + { 2, 0, 1, "sleep", {E}, { Hex0, Hex1, Hex8, Hex0,E}}, + { 2, 2, 1, "stc", {CCR, RD8,E}, { Hex0, Hex2, Hex0, RD8,E}}, + { 2, 2, 1, "sub.b", {RS8,RD8,E}, { Hex1, Hex8, RS8, RD8,E}}, + { 2, 2, 1, "sub.w", {RS16|B30, RD16|B30,E}, {Hex1, Hex9, RS16|B30, RD16|B30,E}}, + { 2, 2, 1, "subs", {KBIT,RD16|B30,E}, { Hex1, HexB, KBIT, RD16|B30,E}}, + TWOOP("subx",HexB, Hex1, HexE), + TWOOP("xor", HexD, Hex1, Hex5), + { 2, 2, 1,"xorc", {IMM8, CCR,E}, { Hex0, Hex5, IMM8,IGNORE,E}}, + { 2, 0,1, "bad 52", {E, IMM8}, { Hex5, Hex2, IMM8, IGNORE,E}}, + { 2, 0,1, "bad 53", {E, IMM8}, { Hex5, Hex3, IMM8, IGNORE,E}}, + { 2, 0,1, "bad 57", {E, IMM8}, { Hex5, Hex7, IMM8, IGNORE,E}}, + { 2, 0,1, "bad 58", {E, IMM8}, { Hex5, Hex8, IMM8, IGNORE,E}}, + { 2, 0,1, "bad 64", {E, IMM8}, { Hex6, Hex4, IMM8, IGNORE,E}}, + { 2, 0,1, "bad 65", {E, IMM8}, { Hex6, Hex5, IMM8, IGNORE,E}}, + { 2, 0,1, "bad 66", {E, IMM8}, { Hex6, Hex6, IMM8, IGNORE,E}}, + { 2, 0,1, "bad 78", {E, IMM8}, { Hex7, Hex8, IMM8, IGNORE,E}}, + { 2, 0,1, "bad 7a", {E, IMM8}, { Hex7, HexA, IMM8, IGNORE,E}}, + { 2, 0,1, "bad 5c", {E, IMM8}, { Hex5, HexC, IMM8, IGNORE,E}}, + + 0 + } + + + +#endif + +; diff --git a/include/opcode/i860.h b/include/opcode/i860.h new file mode 100644 index 00000000000..c17e1f7f869 --- /dev/null +++ b/include/opcode/i860.h @@ -0,0 +1,491 @@ +/* Table of opcodes for the i860. + Copyright (C) 1989 Free Software Foundation, Inc. + +This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. + +GAS/GDB is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GAS/GDB is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GAS or GDB; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#if !defined(__STDC__) && !defined(const) +#define const +#endif + +/* + * Structure of an opcode table entry. + */ +struct i860_opcode +{ + const char *name; + unsigned long match; /* Bits that must be set. */ + unsigned long lose; /* Bits that must not be set. */ + const char *args; + /* Nonzero if this is a possible expand-instruction. */ + char expand; +}; + +enum expand_type +{ + E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY +}; + +/* + All i860 opcodes are 32 bits, except for the pseudoinstructions + and the operations utilizing a 32-bit address expression, an + unsigned 32-bit constant, or a signed 32-bit constant. + These opcodes are expanded into a two-instruction sequence for + any situation where the immediate operand does not fit in 32 bits. + In the case of the add and subtract operations the expansion is + to a three-instruction sequence (ex: orh, or, adds). In cases + where the address is to be relocated, the instruction is + expanded to handle the worse case, this could be optimized at + the final link if the actual address were known. + + The pseudoinstructions are: mov, fmov, pmov, nop, and fnop. + These instructions are implemented as a one or two instruction + sequence of other operations. + + The match component is a mask saying which bits must match a + particular opcode in order for an instruction to be an instance + of that opcode. + + The args component is a string containing one character + for each operand of the instruction. + +Kinds of operands: + # Number used by optimizer. It is ignored. + 1 src1 integer register. + 2 src2 integer register. + d dest register. + c ctrlreg control register. + i 16 bit immediate. + I 16 bit immediate, aligned. + 5 5 bit immediate. + l lbroff 26 bit PC relative immediate. + r sbroff 16 bit PC relative immediate. + s split 16 bit immediate. + S split 16 bit immediate, aligned. + e src1 floating point register. + f src2 floating point register. + g dest floating point register. + +*/ + +/* The order of the opcodes in this table is significant: + + * The assembler requires that all instances of the same mnemonic must be + consecutive. If they aren't, the assembler will bomb at runtime. + + * The disassembler should not care about the order of the opcodes. */ + +static struct i860_opcode i860_opcodes[] = +{ + +/* REG-Format Instructions */ +{ "ld.c", 0x30000000, 0xcc000000, "c,d", 0 }, /* ld.c csrc2,idest */ +{ "ld.b", 0x00000000, 0xfc000000, "1(2),d", 0 }, /* ld.b isrc1(isrc2),idest */ +{ "ld.b", 0x04000000, 0xf8000000, "I(2),d", E_ADDR }, /* ld.b #const(isrc2),idest */ +{ "ld.s", 0x10000000, 0xec000001, "1(2),d", 0 }, /* ld.s isrc1(isrc2),idest */ +{ "ld.s", 0x14000001, 0xe8000000, "I(2),d", E_ADDR }, /* ld.s #const(isrc2),idest */ +{ "ld.l", 0x10000001, 0xec000000, "1(2),d", 0 }, /* ld.l isrc1(isrc2),idest */ +{ "ld.l", 0x14000001, 0xe8000000, "I(2),d", E_ADDR }, /* ld.l #const(isrc2),idest */ + +{ "st.c", 0x38000000, 0xc4000000, "1,c", 0 }, /* st.c isrc1ni,csrc2 */ +{ "st.b", 0x0c000000, 0xf0000000, "1,S(2)", E_ADDR }, /* st.b isrc1ni,#const(isrc2) */ +{ "st.s", 0x1c000000, 0xe0000000, "1,S(2)", E_ADDR }, /* st.s isrc1ni,#const(isrc2) */ +{ "st.l", 0x1c000001, 0xe0000000, "1,S(2)", E_ADDR }, /* st.l isrc1ni,#const(isrc2) */ + +{ "ixfr", 0x08000000, 0xf4000000, "1,g", 0 }, /* ixfr isrc1ni,fdest */ + +{ "fld.l", 0x20000002, 0xdc000001, "1(2),g", 0 }, /* fld.l isrc1(isrc2),fdest */ +{ "fld.l", 0x24000002, 0xd8000001, "i(2),g", E_ADDR }, /* fld.l #const(isrc2),fdest */ +{ "fld.l", 0x20000003, 0xdc000000, "1(2)++,g", 0 }, /* fld.l isrc1(isrc2)++,fdest */ +{ "fld.l", 0x24000003, 0xd8000000, "i(2)++,g", E_ADDR }, /* fld.l #const(isrc2)++,fdest */ +{ "fld.d", 0x20000000, 0xdc000007, "1(2),g", 0 }, /* fld.d isrc1(isrc2),fdest */ +{ "fld.d", 0x24000000, 0xd8000007, "i(2),g", E_ADDR }, /* fld.d #const(isrc2),fdest */ +{ "fld.d", 0x20000001, 0xdc000006, "1(2)++,g", 0 }, /* fld.d isrc1(isrc2)++,fdest */ +{ "fld.d", 0x24000001, 0xd8000006, "i(2)++,g", E_ADDR }, /* fld.d #const(isrc2)++,fdest */ +{ "fld.q", 0x20000004, 0xdc000003, "1(2),g", 0 }, /* fld.q isrc1(isrc2),fdest */ +{ "fld.q", 0x24000004, 0xd8000003, "i(2),g", E_ADDR }, /* fld.q #const(isrc2),fdest */ +{ "fld.q", 0x20000005, 0xdc000002, "1(2)++,g", 0 }, /* fld.q isrc1(isrc2)++,fdest */ +{ "fld.q", 0x24000005, 0xd8000002, "i(2)++,g", E_ADDR }, /* fld.q #const(isrc2)++,fdest */ + +{ "pfld.l", 0x60000000, 0x9c000003, "1(2),g", 0 }, /* pfld.l isrc1(isrc2),fdest */ +{ "pfld.l", 0x64000000, 0x98000003, "i(2),g", E_ADDR }, /* pfld.l #const(isrc2),fdest */ +{ "pfld.l", 0x60000001, 0x9c000002, "1(2)++,g", 0 }, /* pfld.l isrc1(isrc2)++,fdest */ +{ "pfld.l", 0x64000001, 0x98000002, "i(2)++,g", E_ADDR }, /* pfld.l #const(isrc2)++,fdest */ +{ "pfld.d", 0x60000000, 0x9c000007, "1(2),g", 0 }, /* pfld.d isrc1(isrc2),fdest */ +{ "pfld.d", 0x64000000, 0x98000007, "i(2),g", E_ADDR }, /* pfld.d #const(isrc2),fdest */ +{ "pfld.d", 0x60000001, 0x9c000006, "1(2)++,g", 0 }, /* pfld.d isrc1(isrc2)++,fdest */ +{ "pfld.d", 0x64000001, 0x98000006, "i(2)++,g", E_ADDR }, /* pfld.d #const(isrc2)++,fdest */ + +{ "fst.l", 0x28000002, 0xd4000001, "g,1(2)", 0 }, /* fst.l fdest,isrc1(isrc2) */ +{ "fst.l", 0x2c000002, 0xd0000001, "g,i(2)", E_ADDR }, /* fst.l fdest,#const(isrc2) */ +{ "fst.l", 0x28000003, 0xd4000000, "g,1(2)++", 0 }, /* fst.l fdest,isrc1(isrc2)++ */ +{ "fst.l", 0x2c000003, 0xd0000000, "g,i(2)++", E_ADDR }, /* fst.l fdest,#const(isrc2)++ */ +{ "fst.d", 0x28000000, 0xd4000007, "g,1(2)", 0 }, /* fst.d fdest,isrc1(isrc2) */ +{ "fst.d", 0x2c000000, 0xd0000007, "g,i(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */ +{ "fst.d", 0x28000001, 0xd4000006, "g,1(2)++", 0 }, /* fst.d fdest,isrc1(isrc2)++ */ +{ "fst.d", 0x2c000001, 0xd0000006, "g,i(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */ + +{ "pst.d", 0x3c000000, 0xc0000007, "g,i(2)", E_ADDR }, /* pst.d fdest,#const(isrc2) */ +{ "pst.d", 0x3c000001, 0xc0000006, "g,i(2)++", E_ADDR }, /* pst.d fdest,#const(isrc2)++ */ + +{ "addu", 0x80000000, 0x7c000000, "1,2,d", 0 }, /* addu isrc1,isrc2,idest */ +{ "addu", 0x84000000, 0x78000000, "i,2,d", E_S32 }, /* addu #const,isrc2,idest */ +{ "adds", 0x90000000, 0x6c000000, "1,2,d", 0 }, /* adds isrc1,isrc2,idest */ +{ "adds", 0x94000000, 0x68000000, "i,2,d", E_S32 }, /* adds #const,isrc2,idest */ +{ "subu", 0x88000000, 0x74000000, "1,2,d", 0 }, /* subu isrc1,isrc2,idest */ +{ "subu", 0x8c000000, 0x70000000, "i,2,d", E_S32 }, /* subu #const,isrc2,idest */ +{ "subs", 0x98000000, 0x64000000, "1,2,d", 0 }, /* subs isrc1,isrc2,idest */ +{ "subs", 0x9c000000, 0x60000000, "i,2,d", E_S32 }, /* subs #const,isrc2,idest */ + +{ "shl", 0xa0000000, 0x5c000000, "1,2,d", 0 }, /* shl isrc1,isrc2,idest */ +{ "shl", 0xa4000000, 0x58000000, "i,2,d", 0 }, /* shl #const,isrc2,idest */ +{ "shr", 0xa8000000, 0x54000000, "1,2,d", 0 }, /* shr isrc1,isrc2,idest */ +{ "shr", 0xac000000, 0x50000000, "i,2,d", 0 }, /* shr #const,isrc2,idest */ +{ "shrd", 0xb0000000, 0x4c000000, "1,2,d", 0 }, /* shrd isrc1,isrc2,idest */ +{ "shra", 0xb8000000, 0x44000000, "1,2,d", 0 }, /* shra isrc1,isrc2,idest */ +{ "shra", 0xbc000000, 0x40000000, "i,2,d", 0 }, /* shra #const,isrc2,idest */ + +{ "mov", 0xa0000000, 0x5c00f800, "2,d", 0 }, /* shl r0,isrc2,idest */ +{ "mov", 0x94000000, 0x69e00000, "i,d", E_MOV }, /* adds #const,r0,idest */ +{ "nop", 0xa0000000, 0x5ffff800, "", 0 }, /* shl r0,r0,r0 */ +{ "fnop", 0xb0000000, 0x4ffff800, "", 0 }, /* shrd r0,r0,r0 */ + +{ "trap", 0x44000000, 0xb8000000, "1,2,d", 0 }, /* trap isrc1ni,isrc2,idest */ + +{ "flush", 0x34000000, 0xc81f0001, "i(2)", E_ADDR }, /* flush #const(isrc2) */ +{ "flush", 0x34000001, 0xc81f0000, "i(2)++", E_ADDR }, /* flush #const(isrc2)++ */ + +{ "and", 0xc0000000, 0x3c000000, "1,2,d", 0 }, /* and isrc1,isrc2,idest */ +{ "and", 0xc4000000, 0x38000000, "i,2,d", E_AND }, /* and #const,isrc2,idest */ +{ "andh", 0xc8000000, 0x34000000, "1,2,d", 0 }, /* andh isrc1,isrc2,idest */ +{ "andh", 0xcc000000, 0x30000000, "i,2,d", 0 }, /* andh #const,isrc2,idest */ +{ "andnot", 0xd0000000, 0x2c000000, "1,2,d", 0 }, /* andnot isrc1,isrc2,idest */ +{ "andnot", 0xd4000000, 0x28000000, "i,2,d", E_U32 }, /* andnot #const,isrc2,idest */ +{ "andnoth", 0xd8000000, 0x24000000, "1,2,d", 0 }, /* andnoth isrc1,isrc2,idest */ +{ "andnoth", 0xdc000000, 0x20000000, "i,2,d", 0 }, /* andnoth #const,isrc2,idest */ +{ "or", 0xe0000000, 0x1c000000, "1,2,d", 0 }, /* or isrc1,isrc2,idest */ +{ "or", 0xe4000000, 0x18000000, "i,2,d", E_U32 }, /* or #const,isrc2,idest */ +{ "orh", 0xe8000000, 0x14000000, "1,2,d", 0 }, /* orh isrc1,isrc2,idest */ +{ "orh", 0xec000000, 0x10000000, "i,2,d", 0 }, /* orh #const,isrc2,idest */ +{ "xor", 0xf0000000, 0x0c000000, "1,2,d", 0 }, /* xor isrc1,isrc2,idest */ +{ "xor", 0xf4000000, 0x08000000, "i,2,d", E_U32 }, /* xor #const,isrc2,idest */ +{ "xorh", 0xf8000000, 0x04000000, "1,2,d", 0 }, /* xorh isrc1,isrc2,idest */ +{ "xorh", 0xfc000000, 0x00000000, "i,2,d", 0 }, /* xorh #const,isrc2,idest */ + +{ "bte", 0x58000000, 0xa4000000, "1,2,s", 0 }, /* bte isrc1s,isrc2,sbroff */ +{ "bte", 0x5c000000, 0xa0000000, "5,2,s", 0 }, /* bte #const5,isrc2,sbroff */ +{ "btne", 0x50000000, 0xac000000, "1,2,s", 0 }, /* btne isrc1s,isrc2,sbroff */ +{ "btne", 0x54000000, 0xa8000000, "5,2,s", 0 }, /* btne #const5,isrc2,sbroff */ +{ "bla", 0xb4000000, 0x48000000, "1,2,s", E_DELAY }, /* bla isrc1s,isrc2,sbroff */ +{ "bri", 0x40000000, 0xbc000000, "1", E_DELAY }, /* bri isrc1ni */ + +/* Core Escape Instruction Format */ +{ "lock", 0x4c000001, 0xb000001e, "", 0 }, /* lock set BL in dirbase */ +{ "calli", 0x4c000002, 0xb000001d, "1", E_DELAY }, /* calli isrc1ni */ +{ "intovr", 0x4c000004, 0xb000001b, "", 0 }, /* intovr trap on integer overflow */ +{ "unlock", 0x4c000007, 0xb0000018, "", 0 }, /* unlock clear BL in dirbase */ + +/* CTRL-Format Instructions */ +{ "br", 0x68000000, 0x94000000, "l", E_DELAY }, /* br lbroff */ +{ "call", 0x6c000000, 0x90000000, "l", E_DELAY }, /* call lbroff */ +{ "bc", 0x70000000, 0x8c000000, "l", 0 }, /* bc lbroff */ +{ "bc.t", 0x74000000, 0x88000000, "l", E_DELAY }, /* bc.t lbroff */ +{ "bnc", 0x78000000, 0x84000000, "l", 0 }, /* bnc lbroff */ +{ "bnc.t", 0x7c000000, 0x80000000, "l", E_DELAY }, /* bnc.t lbroff */ + +/* Floating Point Escape Instruction Format - pfam.p fsrc1,fsrc2,fdest */ +{ "r2p1.ss", 0x48000400, 0xb40003ff, "e,f,g", 0 }, +{ "r2p1.sd", 0x48000480, 0xb400037f, "e,f,g", 0 }, +{ "r2p1.dd", 0x48000580, 0xb400027f, "e,f,g", 0 }, +{ "r2pt.ss", 0x48000401, 0xb40003fe, "e,f,g", 0 }, +{ "r2pt.sd", 0x48000481, 0xb400037e, "e,f,g", 0 }, +{ "r2pt.dd", 0x48000581, 0xb400027e, "e,f,g", 0 }, +{ "r2ap1.ss", 0x48000402, 0xb40003fd, "e,f,g", 0 }, +{ "r2ap1.sd", 0x48000482, 0xb400037d, "e,f,g", 0 }, +{ "r2ap1.dd", 0x48000582, 0xb400027d, "e,f,g", 0 }, +{ "r2apt.ss", 0x48000403, 0xb40003fc, "e,f,g", 0 }, +{ "r2apt.sd", 0x48000483, 0xb400037c, "e,f,g", 0 }, +{ "r2apt.dd", 0x48000583, 0xb400027c, "e,f,g", 0 }, +{ "i2p1.ss", 0x48000404, 0xb40003fb, "e,f,g", 0 }, +{ "i2p1.sd", 0x48000484, 0xb400037b, "e,f,g", 0 }, +{ "i2p1.dd", 0x48000584, 0xb400027b, "e,f,g", 0 }, +{ "i2pt.ss", 0x48000405, 0xb40003fa, "e,f,g", 0 }, +{ "i2pt.sd", 0x48000485, 0xb400037a, "e,f,g", 0 }, +{ "i2pt.dd", 0x48000585, 0xb400027a, "e,f,g", 0 }, +{ "i2ap1.ss", 0x48000406, 0xb40003f9, "e,f,g", 0 }, +{ "i2ap1.sd", 0x48000486, 0xb4000379, "e,f,g", 0 }, +{ "i2ap1.dd", 0x48000586, 0xb4000279, "e,f,g", 0 }, +{ "i2apt.ss", 0x48000407, 0xb40003f8, "e,f,g", 0 }, +{ "i2apt.sd", 0x48000487, 0xb4000378, "e,f,g", 0 }, +{ "i2apt.dd", 0x48000587, 0xb4000278, "e,f,g", 0 }, +{ "rat1p2.ss", 0x48000408, 0xb40003f7, "e,f,g", 0 }, +{ "rat1p2.sd", 0x48000488, 0xb4000377, "e,f,g", 0 }, +{ "rat1p2.dd", 0x48000588, 0xb4000277, "e,f,g", 0 }, +{ "m12apm.ss", 0x48000409, 0xb40003f6, "e,f,g", 0 }, +{ "m12apm.sd", 0x48000489, 0xb4000376, "e,f,g", 0 }, +{ "m12apm.dd", 0x48000589, 0xb4000276, "e,f,g", 0 }, +{ "ra1p2.ss", 0x4800040a, 0xb40003f5, "e,f,g", 0 }, +{ "ra1p2.sd", 0x4800048a, 0xb4000375, "e,f,g", 0 }, +{ "ra1p2.dd", 0x4800058a, 0xb4000275, "e,f,g", 0 }, +{ "m12ttpa.ss", 0x4800040b, 0xb40003f4, "e,f,g", 0 }, +{ "m12ttpa.sd", 0x4800048b, 0xb4000374, "e,f,g", 0 }, +{ "m12ttpa.dd", 0x4800058b, 0xb4000274, "e,f,g", 0 }, +{ "iat1p2.ss", 0x4800040c, 0xb40003f3, "e,f,g", 0 }, +{ "iat1p2.sd", 0x4800048c, 0xb4000373, "e,f,g", 0 }, +{ "iat1p2.dd", 0x4800058c, 0xb4000273, "e,f,g", 0 }, +{ "m12tpm.ss", 0x4800040d, 0xb40003f2, "e,f,g", 0 }, +{ "m12tpm.sd", 0x4800048d, 0xb4000372, "e,f,g", 0 }, +{ "m12tpm.dd", 0x4800058d, 0xb4000272, "e,f,g", 0 }, +{ "ia1p2.ss", 0x4800040e, 0xb40003f1, "e,f,g", 0 }, +{ "ia1p2.sd", 0x4800048e, 0xb4000371, "e,f,g", 0 }, +{ "ia1p2.dd", 0x4800058e, 0xb4000271, "e,f,g", 0 }, +{ "m12tpa.ss", 0x4800040f, 0xb40003f0, "e,f,g", 0 }, +{ "m12tpa.sd", 0x4800048f, 0xb4000370, "e,f,g", 0 }, +{ "m12tpa.dd", 0x4800058f, 0xb4000270, "e,f,g", 0 }, + +/* Floating Point Escape Instruction Format - pfsm.p fsrc1,fsrc2,fdest */ +{ "r2s1.ss", 0x48000410, 0xb40003ef, "e,f,g", 0 }, +{ "r2s1.sd", 0x48000490, 0xb400036f, "e,f,g", 0 }, +{ "r2s1.dd", 0x48000590, 0xb400026f, "e,f,g", 0 }, +{ "r2st.ss", 0x48000411, 0xb40003ee, "e,f,g", 0 }, +{ "r2st.sd", 0x48000491, 0xb400036e, "e,f,g", 0 }, +{ "r2st.dd", 0x48000591, 0xb400026e, "e,f,g", 0 }, +{ "r2as1.ss", 0x48000412, 0xb40003ed, "e,f,g", 0 }, +{ "r2as1.sd", 0x48000492, 0xb400036d, "e,f,g", 0 }, +{ "r2as1.dd", 0x48000592, 0xb400026d, "e,f,g", 0 }, +{ "r2ast.ss", 0x48000413, 0xb40003ec, "e,f,g", 0 }, +{ "r2ast.sd", 0x48000493, 0xb400036c, "e,f,g", 0 }, +{ "r2ast.dd", 0x48000593, 0xb400026c, "e,f,g", 0 }, +{ "i2s1.ss", 0x48000414, 0xb40003eb, "e,f,g", 0 }, +{ "i2s1.sd", 0x48000494, 0xb400036b, "e,f,g", 0 }, +{ "i2s1.dd", 0x48000594, 0xb400026b, "e,f,g", 0 }, +{ "i2st.ss", 0x48000415, 0xb40003ea, "e,f,g", 0 }, +{ "i2st.sd", 0x48000495, 0xb400036a, "e,f,g", 0 }, +{ "i2st.dd", 0x48000595, 0xb400026a, "e,f,g", 0 }, +{ "i2as1.ss", 0x48000416, 0xb40003e9, "e,f,g", 0 }, +{ "i2as1.sd", 0x48000496, 0xb4000369, "e,f,g", 0 }, +{ "i2as1.dd", 0x48000596, 0xb4000269, "e,f,g", 0 }, +{ "i2ast.ss", 0x48000417, 0xb40003e8, "e,f,g", 0 }, +{ "i2ast.sd", 0x48000497, 0xb4000368, "e,f,g", 0 }, +{ "i2ast.dd", 0x48000597, 0xb4000268, "e,f,g", 0 }, +{ "rat1s2.ss", 0x48000418, 0xb40003e7, "e,f,g", 0 }, +{ "rat1s2.sd", 0x48000498, 0xb4000367, "e,f,g", 0 }, +{ "rat1s2.dd", 0x48000598, 0xb4000267, "e,f,g", 0 }, +{ "m12asm.ss", 0x48000419, 0xb40003e6, "e,f,g", 0 }, +{ "m12asm.sd", 0x48000499, 0xb4000366, "e,f,g", 0 }, +{ "m12asm.dd", 0x48000599, 0xb4000266, "e,f,g", 0 }, +{ "ra1s2.ss", 0x4800041a, 0xb40003e5, "e,f,g", 0 }, +{ "ra1s2.sd", 0x4800049a, 0xb4000365, "e,f,g", 0 }, +{ "ra1s2.dd", 0x4800059a, 0xb4000265, "e,f,g", 0 }, +{ "m12ttsa.ss", 0x4800041b, 0xb40003e4, "e,f,g", 0 }, +{ "m12ttsa.sd", 0x4800049b, 0xb4000364, "e,f,g", 0 }, +{ "m12ttsa.dd", 0x4800059b, 0xb4000264, "e,f,g", 0 }, +{ "iat1s2.ss", 0x4800041c, 0xb40003e3, "e,f,g", 0 }, +{ "iat1s2.sd", 0x4800049c, 0xb4000363, "e,f,g", 0 }, +{ "iat1s2.dd", 0x4800059c, 0xb4000263, "e,f,g", 0 }, +{ "m12tsm.ss", 0x4800041d, 0xb40003e2, "e,f,g", 0 }, +{ "m12tsm.sd", 0x4800049d, 0xb4000362, "e,f,g", 0 }, +{ "m12tsm.dd", 0x4800059d, 0xb4000262, "e,f,g", 0 }, +{ "ia1s2.ss", 0x4800041e, 0xb40003e1, "e,f,g", 0 }, +{ "ia1s2.sd", 0x4800049e, 0xb4000361, "e,f,g", 0 }, +{ "ia1s2.dd", 0x4800059e, 0xb4000261, "e,f,g", 0 }, +{ "m12tsa.ss", 0x4800041f, 0xb40003e0, "e,f,g", 0 }, +{ "m12tsa.sd", 0x4800049f, 0xb4000360, "e,f,g", 0 }, +{ "m12tsa.dd", 0x4800059f, 0xb4000260, "e,f,g", 0 }, + +/* Floating Point Escape Instruction Format - pfmam.p fsrc1,fsrc2,fdest */ +{ "mr2p1.ss", 0x48000000, 0xb40007ff, "e,f,g", 0 }, +{ "mr2p1.sd", 0x48000080, 0xb400077f, "e,f,g", 0 }, +{ "mr2p1.dd", 0x48000180, 0xb400067f, "e,f,g", 0 }, +{ "mr2pt.ss", 0x48000001, 0xb40007fe, "e,f,g", 0 }, +{ "mr2pt.sd", 0x48000081, 0xb400077e, "e,f,g", 0 }, +{ "mr2pt.dd", 0x48000181, 0xb400067e, "e,f,g", 0 }, +{ "mr2mp1.ss", 0x48000002, 0xb40007fd, "e,f,g", 0 }, +{ "mr2mp1.sd", 0x48000082, 0xb400077d, "e,f,g", 0 }, +{ "mr2mp1.dd", 0x48000182, 0xb400067d, "e,f,g", 0 }, +{ "mr2mpt.ss", 0x48000003, 0xb40007fc, "e,f,g", 0 }, +{ "mr2mpt.sd", 0x48000083, 0xb400077c, "e,f,g", 0 }, +{ "mr2mpt.dd", 0x48000183, 0xb400067c, "e,f,g", 0 }, +{ "mi2p1.ss", 0x48000004, 0xb40007fb, "e,f,g", 0 }, +{ "mi2p1.sd", 0x48000084, 0xb400077b, "e,f,g", 0 }, +{ "mi2p1.dd", 0x48000184, 0xb400067b, "e,f,g", 0 }, +{ "mi2pt.ss", 0x48000005, 0xb40007fa, "e,f,g", 0 }, +{ "mi2pt.sd", 0x48000085, 0xb400077a, "e,f,g", 0 }, +{ "mi2pt.dd", 0x48000185, 0xb400067a, "e,f,g", 0 }, +{ "mi2mp1.ss", 0x48000006, 0xb40007f9, "e,f,g", 0 }, +{ "mi2mp1.sd", 0x48000086, 0xb4000779, "e,f,g", 0 }, +{ "mi2mp1.dd", 0x48000186, 0xb4000679, "e,f,g", 0 }, +{ "mi2mpt.ss", 0x48000007, 0xb40007f8, "e,f,g", 0 }, +{ "mi2mpt.sd", 0x48000087, 0xb4000778, "e,f,g", 0 }, +{ "mi2mpt.dd", 0x48000187, 0xb4000678, "e,f,g", 0 }, +{ "mrmt1p2.ss", 0x48000008, 0xb40007f7, "e,f,g", 0 }, +{ "mrmt1p2.sd", 0x48000088, 0xb4000777, "e,f,g", 0 }, +{ "mrmt1p2.dd", 0x48000188, 0xb4000677, "e,f,g", 0 }, +{ "mm12mpm.ss", 0x48000009, 0xb40007f6, "e,f,g", 0 }, +{ "mm12mpm.sd", 0x48000089, 0xb4000776, "e,f,g", 0 }, +{ "mm12mpm.dd", 0x48000189, 0xb4000676, "e,f,g", 0 }, +{ "mrm1p2.ss", 0x4800000a, 0xb40007f5, "e,f,g", 0 }, +{ "mrm1p2.sd", 0x4800008a, 0xb4000775, "e,f,g", 0 }, +{ "mrm1p2.dd", 0x4800018a, 0xb4000675, "e,f,g", 0 }, +{ "mm12ttpm.ss",0x4800000b, 0xb40007f4, "e,f,g", 0 }, +{ "mm12ttpm.sd",0x4800008b, 0xb4000774, "e,f,g", 0 }, +{ "mm12ttpm.dd",0x4800018b, 0xb4000674, "e,f,g", 0 }, +{ "mimt1p2.ss", 0x4800000c, 0xb40007f3, "e,f,g", 0 }, +{ "mimt1p2.sd", 0x4800008c, 0xb4000773, "e,f,g", 0 }, +{ "mimt1p2.dd", 0x4800018c, 0xb4000673, "e,f,g", 0 }, +{ "mm12tpm.ss", 0x4800000d, 0xb40007f2, "e,f,g", 0 }, +{ "mm12tpm.sd", 0x4800008d, 0xb4000772, "e,f,g", 0 }, +{ "mm12tpm.dd", 0x4800018d, 0xb4000672, "e,f,g", 0 }, +{ "mim1p2.ss", 0x4800000e, 0xb40007f1, "e,f,g", 0 }, +{ "mim1p2.sd", 0x4800008e, 0xb4000771, "e,f,g", 0 }, +{ "mim1p2.dd", 0x4800018e, 0xb4000671, "e,f,g", 0 }, + +/* Floating Point Escape Instruction Format - pfmsm.p fsrc1,fsrc2,fdest */ +{ "mr2s1.ss", 0x48000010, 0xb40007ef, "e,f,g", 0 }, +{ "mr2s1.sd", 0x48000090, 0xb400076f, "e,f,g", 0 }, +{ "mr2s1.dd", 0x48000190, 0xb400066f, "e,f,g", 0 }, +{ "mr2st.ss", 0x48000011, 0xb40007ee, "e,f,g", 0 }, +{ "mr2st.sd", 0x48000091, 0xb400076e, "e,f,g", 0 }, +{ "mr2st.dd", 0x48000191, 0xb400066e, "e,f,g", 0 }, +{ "mr2ms1.ss", 0x48000012, 0xb40007ed, "e,f,g", 0 }, +{ "mr2ms1.sd", 0x48000092, 0xb400076d, "e,f,g", 0 }, +{ "mr2ms1.dd", 0x48000192, 0xb400066d, "e,f,g", 0 }, +{ "mr2mst.ss", 0x48000013, 0xb40007ec, "e,f,g", 0 }, +{ "mr2mst.sd", 0x48000093, 0xb400076c, "e,f,g", 0 }, +{ "mr2mst.dd", 0x48000193, 0xb400066c, "e,f,g", 0 }, +{ "mi2s1.ss", 0x48000014, 0xb40007eb, "e,f,g", 0 }, +{ "mi2s1.sd", 0x48000094, 0xb400076b, "e,f,g", 0 }, +{ "mi2s1.dd", 0x48000194, 0xb400066b, "e,f,g", 0 }, +{ "mi2st.ss", 0x48000015, 0xb40007ea, "e,f,g", 0 }, +{ "mi2st.sd", 0x48000095, 0xb400076a, "e,f,g", 0 }, +{ "mi2st.dd", 0x48000195, 0xb400066a, "e,f,g", 0 }, +{ "mi2ms1.ss", 0x48000016, 0xb40007e9, "e,f,g", 0 }, +{ "mi2ms1.sd", 0x48000096, 0xb4000769, "e,f,g", 0 }, +{ "mi2ms1.dd", 0x48000196, 0xb4000669, "e,f,g", 0 }, +{ "mi2mst.ss", 0x48000017, 0xb40007e8, "e,f,g", 0 }, +{ "mi2mst.sd", 0x48000097, 0xb4000768, "e,f,g", 0 }, +{ "mi2mst.dd", 0x48000197, 0xb4000668, "e,f,g", 0 }, +{ "mrmt1s2.ss", 0x48000018, 0xb40007e7, "e,f,g", 0 }, +{ "mrmt1s2.sd", 0x48000098, 0xb4000767, "e,f,g", 0 }, +{ "mrmt1s2.dd", 0x48000198, 0xb4000667, "e,f,g", 0 }, +{ "mm12msm.ss", 0x48000019, 0xb40007e6, "e,f,g", 0 }, +{ "mm12msm.sd", 0x48000099, 0xb4000766, "e,f,g", 0 }, +{ "mm12msm.dd", 0x48000199, 0xb4000666, "e,f,g", 0 }, +{ "mrm1s2.ss", 0x4800001a, 0xb40007e5, "e,f,g", 0 }, +{ "mrm1s2.sd", 0x4800009a, 0xb4000765, "e,f,g", 0 }, +{ "mrm1s2.dd", 0x4800019a, 0xb4000665, "e,f,g", 0 }, +{ "mm12ttsm.ss",0x4800001b, 0xb40007e4, "e,f,g", 0 }, +{ "mm12ttsm.sd",0x4800009b, 0xb4000764, "e,f,g", 0 }, +{ "mm12ttsm.dd",0x4800019b, 0xb4000664, "e,f,g", 0 }, +{ "mimt1s2.ss", 0x4800001c, 0xb40007e3, "e,f,g", 0 }, +{ "mimt1s2.sd", 0x4800009c, 0xb4000763, "e,f,g", 0 }, +{ "mimt1s2.dd", 0x4800019c, 0xb4000663, "e,f,g", 0 }, +{ "mm12tsm.ss", 0x4800001d, 0xb40007e2, "e,f,g", 0 }, +{ "mm12tsm.sd", 0x4800009d, 0xb4000762, "e,f,g", 0 }, +{ "mm12tsm.dd", 0x4800019d, 0xb4000662, "e,f,g", 0 }, +{ "mim1s2.ss", 0x4800001e, 0xb40007e1, "e,f,g", 0 }, +{ "mim1s2.sd", 0x4800009e, 0xb4000761, "e,f,g", 0 }, +{ "mim1s2.dd", 0x4800019e, 0xb4000661, "e,f,g", 0 }, + + +{ "fmul.ss", 0x48000020, 0xb40007df, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ +{ "fmul.sd", 0x480000a0, 0xb400075f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ +{ "fmul.dd", 0x480001a0, 0xb400065f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ +{ "pfmul.ss", 0x48000420, 0xb40003df, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ +{ "pfmul.sd", 0x480004a0, 0xb400035f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ +{ "pfmul.dd", 0x480005a0, 0xb400025f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ +{ "pfmul3.dd", 0x480005a4, 0xb400025b, "e,f,g", 0 }, /* pfmul3.p fsrc1,fsrc2,fdest */ +{ "fmlow.dd", 0x480001a1, 0xb400065e, "e,f,g", 0 }, /* fmlow.dd fsrc1,fsrc2,fdest */ +{ "frcp.ss", 0x48000022, 0xb40007dd, "f,g", 0 }, /* frcp.p fsrc2,fdest */ +{ "frcp.sd", 0x480000a2, 0xb400075d, "f,g", 0 }, /* frcp.p fsrc2,fdest */ +{ "frcp.dd", 0x480001a2, 0xb400065d, "f,g", 0 }, /* frcp.p fsrc2,fdest */ +{ "frsqr.ss", 0x48000023, 0xb40007dc, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ +{ "frsqr.sd", 0x480000a3, 0xb400075c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ +{ "frsqr.dd", 0x480001a3, 0xb400065c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ +{ "fadd.ss", 0x48000030, 0xb40007cf, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ +{ "fadd.sd", 0x480000b0, 0xb400074f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ +{ "fadd.dd", 0x480001b0, 0xb400064f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ +{ "pfadd.ss", 0x48000430, 0xb40003cf, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ +{ "pfadd.sd", 0x480004b0, 0xb400034f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ +{ "pfadd.dd", 0x480005b0, 0xb400024f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ +{ "fsub.ss", 0x48000031, 0xb40007ce, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ +{ "fsub.sd", 0x480000b1, 0xb400074e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ +{ "fsub.dd", 0x480001b1, 0xb400064e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ +{ "pfsub.ss", 0x48000431, 0xb40003ce, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ +{ "pfsub.sd", 0x480004b1, 0xb400034e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ +{ "pfsub.dd", 0x480005b1, 0xb400024e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ +{ "fix.ss", 0x48000032, 0xb40007cd, "e,g", 0 }, /* fix.p fsrc1,fdest */ +{ "fix.sd", 0x480000b2, 0xb400074d, "e,g", 0 }, /* fix.p fsrc1,fdest */ +{ "fix.dd", 0x480001b2, 0xb400064d, "e,g", 0 }, /* fix.p fsrc1,fdest */ +{ "pfix.ss", 0x48000432, 0xb40003cd, "e,g", 0 }, /* pfix.p fsrc1,fdest */ +{ "pfix.sd", 0x480004b2, 0xb400034d, "e,g", 0 }, /* pfix.p fsrc1,fdest */ +{ "pfix.dd", 0x480005b2, 0xb400024d, "e,g", 0 }, /* pfix.p fsrc1,fdest */ +{ "famov.ss", 0x48000033, 0xb40007cc, "e,g", 0 }, /* famov.p fsrc1,fdest */ +{ "famov.ds", 0x48000133, 0xb40006cc, "e,g", 0 }, /* famov.p fsrc1,fdest */ +{ "famov.sd", 0x480000b3, 0xb400074c, "e,g", 0 }, /* famov.p fsrc1,fdest */ +{ "famov.dd", 0x480001b3, 0xb400064c, "e,g", 0 }, /* famov.p fsrc1,fdest */ +{ "pfamov.ss", 0x48000433, 0xb40003cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ +{ "pfamov.ds", 0x48000533, 0xb40002cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ +{ "pfamov.sd", 0x480004b3, 0xb400034c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ +{ "pfamov.dd", 0x480005b3, 0xb400024c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ +/* pfgt has R bit cleared; pfle has R bit set */ +{ "pfgt.ss", 0x48000434, 0xb40003cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */ +{ "pfgt.sd", 0x48000434, 0xb40003cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */ +{ "pfgt.dd", 0x48000534, 0xb40002cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */ +/* pfgt has R bit cleared; pfle has R bit set */ +{ "pfle.ss", 0x480004b4, 0xb400034b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */ +{ "pfle.sd", 0x480004b4, 0xb400034b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */ +{ "pfle.dd", 0x480005b4, 0xb400024b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */ +{ "ftrunc.ss", 0x4800003a, 0xb40007c5, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */ +{ "ftrunc.sd", 0x480000ba, 0xb4000745, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */ +{ "ftrunc.dd", 0x480001ba, 0xb4000645, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */ +{ "pftrunc.ss", 0x4800043a, 0xb40003c5, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */ +{ "pftrunc.sd", 0x480004ba, 0xb4000345, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */ +{ "pftrunc.dd", 0x480005ba, 0xb4000245, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */ +{ "fxfr", 0x48000040, 0xb40007bf, "e,d", 0 }, /* fxfr fsrc1,idest */ +{ "fiadd.ss", 0x48000049, 0xb40007b6, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */ +{ "fiadd.dd", 0x480001c9, 0xb4000636, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */ +{ "pfiadd.ss", 0x48000449, 0xb40003b6, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */ +{ "pfiadd.dd", 0x480005c9, 0xb4000236, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */ +{ "fisub.ss", 0x4800004d, 0xb40007b2, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */ +{ "fisub.dd", 0x480001cd, 0xb4000632, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */ +{ "pfisub.ss", 0x4800044d, 0xb40003b2, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */ +{ "pfisub.dd", 0x480005cd, 0xb4000232, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */ +{ "fzchkl", 0x48000057, 0xb40007a8, "e,f,g", 0 }, /* fzchkl fsrc1,fsrc2,fdest */ +{ "pfzchkl", 0x48000457, 0xb40003a8, "e,f,g", 0 }, /* pfzchkl fsrc1,fsrc2,fdest */ +{ "fzchks", 0x4800005f, 0xb40007a0, "e,f,g", 0 }, /* fzchks fsrc1,fsrc2,fdest */ +{ "pfzchks", 0x4800045f, 0xb40003a0, "e,f,g", 0 }, /* pfzchks fsrc1,fsrc2,fdest */ +{ "faddp", 0x48000050, 0xb40007af, "e,f,g", 0 }, /* faddp fsrc1,fsrc2,fdest */ +{ "pfaddp", 0x48000450, 0xb40003af, "e,f,g", 0 }, /* pfaddp fsrc1,fsrc2,fdest */ +{ "faddz", 0x48000051, 0xb40007ae, "e,f,g", 0 }, /* faddz fsrc1,fsrc2,fdest */ +{ "pfaddz", 0x48000451, 0xb40003ae, "e,f,g", 0 }, /* pfaddz fsrc1,fsrc2,fdest */ +{ "form", 0x4800005a, 0xb40007a5, "e,g", 0 }, /* form fsrc1,fdest */ +{ "pform", 0x4800045a, 0xb40003a5, "e,g", 0 }, /* pform fsrc1,fdest */ + +/* Floating point pseudo-instructions */ +{ "fmov.ss", 0x48000049, 0xb7e007b6, "e,g", 0 }, /* fiadd.ss fsrc1,f0,fdest */ +{ "fmov.dd", 0x480001c9, 0xb7e00636, "e,g", 0 }, /* fiadd.dd fsrc1,f0,fdest */ +{ "fmov.sd", 0x480000b0, 0xb7e0074f, "e,g", 0 }, /* fadd.sd fsrc1,f0,fdest */ +{ "fmov.ds", 0x48000130, 0xb7e006cf, "e,g", 0 }, /* fadd.ds fsrc1,f0,fdest */ +{ "pfmov.ds", 0x48000530, 0xb73002cf, "e,g", 0 }, /* pfadd.ds fsrc1,f0,fdest */ +{ "pfmov.dd", 0x480005c9, 0xb7e00236, "e,g", 0 }, /* pfiadd.dd fsrc1,f0,fdest */ + + +}; + +#define NUMOPCODES ((sizeof i860_opcodes)/(sizeof i860_opcodes[0])) + + diff --git a/include/opcode/np1.h b/include/opcode/np1.h new file mode 100644 index 00000000000..654682570fa --- /dev/null +++ b/include/opcode/np1.h @@ -0,0 +1,422 @@ +/* Print GOULD NPL instructions for GDB, the GNU debugger. + Copyright (C) 1986, 1987, 1989 Free Software Foundation, Inc. + +This file is part of GDB. + +GDB is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GDB is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GDB; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +struct gld_opcode +{ + char *name; + unsigned long opcode; + unsigned long mask; + char *args; + int length; +}; + +/* We store four bytes of opcode for all opcodes because that + is the most any of them need. The actual length of an instruction + is always at least 2 bytes, and at most four. The length of the + instruction is based on the opcode. + + The mask component is a mask saying which bits must match + particular opcode in order for an instruction to be an instance + of that opcode. + + The args component is a string containing characters + that are used to format the arguments to the instruction. */ + +/* Kinds of operands: + r Register in first field + R Register in second field + b Base register in first field + B Base register in second field + v Vector register in first field + V Vector register in first field + A Optional address register (base register) + X Optional index register + I Immediate data (16bits signed) + O Offset field (16bits signed) + h Offset field (15bits signed) + d Offset field (14bits signed) + S Shift count field + + any other characters are printed as is... +*/ + +/* The assembler requires that this array be sorted as follows: + all instances of the same mnemonic must be consecutive. + All instances of the same mnemonic with the same number of operands + must be consecutive. + */ +struct gld_opcode gld_opcodes[] = +{ +{ "lb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "lnb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "lbs", 0xec080000, 0xfc080000, "r,xOA,X", 4 }, +{ "lh", 0xb4000001, 0xfc080001, "r,xOA,X", 4 }, +{ "lnh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "lw", 0xb4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lnw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "ld", 0xb4000002, 0xfc080002, "r,xOA,X", 4 }, +{ "lnd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "li", 0xf8000000, 0xfc7f0000, "r,I", 4 }, +{ "lpa", 0x50080000, 0xfc080000, "r,xOA,X", 4 }, +{ "la", 0x50000000, 0xfc080000, "r,xOA,X", 4 }, +{ "labr", 0x58080000, 0xfc080000, "b,xOA,X", 4 }, +{ "lbp", 0x90080000, 0xfc080000, "r,xOA,X", 4 }, +{ "lhp", 0x90000001, 0xfc080001, "r,xOA,X", 4 }, +{ "lwp", 0x90000000, 0xfc080000, "r,xOA,X", 4 }, +{ "ldp", 0x90000002, 0xfc080002, "r,xOA,X", 4 }, +{ "suabr", 0x58000000, 0xfc080000, "b,xOA,X", 4 }, +{ "lf", 0xbc000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lfbr", 0xbc080000, 0xfc080000, "b,xOA,X", 4 }, +{ "lwbr", 0x5c000000, 0xfc080000, "b,xOA,X", 4 }, +{ "stb", 0xd4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "sth", 0xd4000001, 0xfc080001, "r,xOA,X", 4 }, +{ "stw", 0xd4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "std", 0xd4000002, 0xfc080002, "r,xOA,X", 4 }, +{ "stf", 0xdc000000, 0xfc080000, "r,xOA,X", 4 }, +{ "stfbr", 0xdc080000, 0xfc080000, "b,xOA,X", 4 }, +{ "stwbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, +{ "zmb", 0xd8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "zmh", 0xd8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "zmw", 0xd8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "zmd", 0xd8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "stbp", 0x94080000, 0xfc080000, "r,xOA,X", 4 }, +{ "sthp", 0x94000001, 0xfc080001, "r,xOA,X", 4 }, +{ "stwp", 0x94000000, 0xfc080000, "r,xOA,X", 4 }, +{ "stdp", 0x94000002, 0xfc080002, "r,xOA,X", 4 }, +{ "lil", 0xf80b0000, 0xfc7f0000, "r,D", 4 }, +{ "lwsl1", 0xec000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lwsl2", 0xfc000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lwsl3", 0xfc080000, 0xfc080000, "r,xOA,X", 4 }, + +{ "lvb", 0xb0080000, 0xfc080000, "v,xOA,X", 4 }, +{ "lvh", 0xb0000001, 0xfc080001, "v,xOA,X", 4 }, +{ "lvw", 0xb0000000, 0xfc080000, "v,xOA,X", 4 }, +{ "lvd", 0xb0000002, 0xfc080002, "v,xOA,X", 4 }, +{ "liv", 0x3c040000, 0xfc0f0000, "v,R", 2 }, +{ "livf", 0x3c080000, 0xfc0f0000, "v,R", 2 }, +{ "stvb", 0xd0080000, 0xfc080000, "v,xOA,X", 4 }, +{ "stvh", 0xd0000001, 0xfc080001, "v,xOA,X", 4 }, +{ "stvw", 0xd0000000, 0xfc080000, "v,xOA,X", 4 }, +{ "stvd", 0xd0000002, 0xfc080002, "v,xOA,X", 4 }, + +{ "trr", 0x2c000000, 0xfc0f0000, "r,R", 2 }, +{ "trn", 0x2c040000, 0xfc0f0000, "r,R", 2 }, +{ "trnd", 0x2c0c0000, 0xfc0f0000, "r,R", 2 }, +{ "trabs", 0x2c010000, 0xfc0f0000, "r,R", 2 }, +{ "trabsd", 0x2c090000, 0xfc0f0000, "r,R", 2 }, +{ "trc", 0x2c030000, 0xfc0f0000, "r,R", 2 }, +{ "xcr", 0x28040000, 0xfc0f0000, "r,R", 2 }, +{ "cxcr", 0x2c060000, 0xfc0f0000, "r,R", 2 }, +{ "cxcrd", 0x2c0e0000, 0xfc0f0000, "r,R", 2 }, +{ "tbrr", 0x2c020000, 0xfc0f0000, "r,B", 2 }, +{ "trbr", 0x28030000, 0xfc0f0000, "b,R", 2 }, +{ "xcbr", 0x28020000, 0xfc0f0000, "b,B", 2 }, +{ "tbrbr", 0x28010000, 0xfc0f0000, "b,B", 2 }, + +{ "trvv", 0x28050000, 0xfc0f0000, "v,V", 2 }, +{ "trvvn", 0x2c050000, 0xfc0f0000, "v,V", 2 }, +{ "trvvnd", 0x2c0d0000, 0xfc0f0000, "v,V", 2 }, +{ "trvab", 0x2c070000, 0xfc0f0000, "v,V", 2 }, +{ "trvabd", 0x2c0f0000, 0xfc0f0000, "v,V", 2 }, +{ "cmpv", 0x14060000, 0xfc0f0000, "v,V", 2 }, +{ "expv", 0x14070000, 0xfc0f0000, "v,V", 2 }, +{ "mrvvlt", 0x10030000, 0xfc0f0000, "v,V", 2 }, +{ "mrvvle", 0x10040000, 0xfc0f0000, "v,V", 2 }, +{ "mrvvgt", 0x14030000, 0xfc0f0000, "v,V", 2 }, +{ "mrvvge", 0x14040000, 0xfc0f0000, "v,V", 2 }, +{ "mrvveq", 0x10050000, 0xfc0f0000, "v,V", 2 }, +{ "mrvvne", 0x10050000, 0xfc0f0000, "v,V", 2 }, +{ "mrvrlt", 0x100d0000, 0xfc0f0000, "v,R", 2 }, +{ "mrvrle", 0x100e0000, 0xfc0f0000, "v,R", 2 }, +{ "mrvrgt", 0x140d0000, 0xfc0f0000, "v,R", 2 }, +{ "mrvrge", 0x140e0000, 0xfc0f0000, "v,R", 2 }, +{ "mrvreq", 0x100f0000, 0xfc0f0000, "v,R", 2 }, +{ "mrvrne", 0x140f0000, 0xfc0f0000, "v,R", 2 }, +{ "trvr", 0x140b0000, 0xfc0f0000, "r,V", 2 }, +{ "trrv", 0x140c0000, 0xfc0f0000, "v,R", 2 }, + +{ "bu", 0x40000000, 0xff880000, "xOA,X", 4 }, +{ "bns", 0x70080000, 0xff880000, "xOA,X", 4 }, +{ "bnco", 0x70880000, 0xff880000, "xOA,X", 4 }, +{ "bge", 0x71080000, 0xff880000, "xOA,X", 4 }, +{ "bne", 0x71880000, 0xff880000, "xOA,X", 4 }, +{ "bunge", 0x72080000, 0xff880000, "xOA,X", 4 }, +{ "bunle", 0x72880000, 0xff880000, "xOA,X", 4 }, +{ "bgt", 0x73080000, 0xff880000, "xOA,X", 4 }, +{ "bnany", 0x73880000, 0xff880000, "xOA,X", 4 }, +{ "bs" , 0x70000000, 0xff880000, "xOA,X", 4 }, +{ "bco", 0x70800000, 0xff880000, "xOA,X", 4 }, +{ "blt", 0x71000000, 0xff880000, "xOA,X", 4 }, +{ "beq", 0x71800000, 0xff880000, "xOA,X", 4 }, +{ "buge", 0x72000000, 0xff880000, "xOA,X", 4 }, +{ "bult", 0x72800000, 0xff880000, "xOA,X", 4 }, +{ "ble", 0x73000000, 0xff880000, "xOA,X", 4 }, +{ "bany", 0x73800000, 0xff880000, "xOA,X", 4 }, +{ "brlnk", 0x44000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bib", 0x48000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bih", 0x48080000, 0xfc080000, "r,xOA,X", 4 }, +{ "biw", 0x4c000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bid", 0x4c080000, 0xfc080000, "r,xOA,X", 4 }, +{ "bivb", 0x60000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bivh", 0x60080000, 0xfc080000, "r,xOA,X", 4 }, +{ "bivw", 0x64000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bivd", 0x64080000, 0xfc080000, "r,xOA,X", 4 }, +{ "bvsb", 0x68000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bvsh", 0x68080000, 0xfc080000, "r,xOA,X", 4 }, +{ "bvsw", 0x6c000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bvsd", 0x6c080000, 0xfc080000, "r,xOA,X", 4 }, + +{ "camb", 0x80080000, 0xfc080000, "r,xOA,X", 4 }, +{ "camh", 0x80000001, 0xfc080001, "r,xOA,X", 4 }, +{ "camw", 0x80000000, 0xfc080000, "r,xOA,X", 4 }, +{ "camd", 0x80000002, 0xfc080002, "r,xOA,X", 4 }, +{ "car", 0x10000000, 0xfc0f0000, "r,R", 2 }, +{ "card", 0x14000000, 0xfc0f0000, "r,R", 2 }, +{ "ci", 0xf8050000, 0xfc7f0000, "r,I", 4 }, +{ "chkbnd", 0x5c080000, 0xfc080000, "r,xOA,X", 4 }, + +{ "cavv", 0x10010000, 0xfc0f0000, "v,V", 2 }, +{ "cavr", 0x10020000, 0xfc0f0000, "v,R", 2 }, +{ "cavvd", 0x10090000, 0xfc0f0000, "v,V", 2 }, +{ "cavrd", 0x100b0000, 0xfc0f0000, "v,R", 2 }, + +{ "anmb", 0x84080000, 0xfc080000, "r,xOA,X", 4 }, +{ "anmh", 0x84000001, 0xfc080001, "r,xOA,X", 4 }, +{ "anmw", 0x84000000, 0xfc080000, "r,xOA,X", 4 }, +{ "anmd", 0x84000002, 0xfc080002, "r,xOA,X", 4 }, +{ "anr", 0x04000000, 0xfc0f0000, "r,R", 2 }, +{ "ani", 0xf8080000, 0xfc7f0000, "r,I", 4 }, +{ "ormb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "ormh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "ormw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "ormd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "orr", 0x08000000, 0xfc0f0000, "r,R", 2 }, +{ "oi", 0xf8090000, 0xfc7f0000, "r,I", 4 }, +{ "eomb", 0x8c080000, 0xfc080000, "r,xOA,X", 4 }, +{ "eomh", 0x8c000001, 0xfc080001, "r,xOA,X", 4 }, +{ "eomw", 0x8c000000, 0xfc080000, "r,xOA,X", 4 }, +{ "eomd", 0x8c000002, 0xfc080002, "r,xOA,X", 4 }, +{ "eor", 0x0c000000, 0xfc0f0000, "r,R", 2 }, +{ "eoi", 0xf80a0000, 0xfc7f0000, "r,I", 4 }, + +{ "anvv", 0x04010000, 0xfc0f0000, "v,V", 2 }, +{ "anvr", 0x04020000, 0xfc0f0000, "v,R", 2 }, +{ "orvv", 0x08010000, 0xfc0f0000, "v,V", 2 }, +{ "orvr", 0x08020000, 0xfc0f0000, "v,R", 2 }, +{ "eovv", 0x0c010000, 0xfc0f0000, "v,V", 2 }, +{ "eovr", 0x0c020000, 0xfc0f0000, "v,R", 2 }, + +{ "sacz", 0x100c0000, 0xfc0f0000, "r,R", 2 }, +{ "sla", 0x1c400000, 0xfc600000, "r,S", 2 }, +{ "sll", 0x1c600000, 0xfc600000, "r,S", 2 }, +{ "slc", 0x24400000, 0xfc600000, "r,S", 2 }, +{ "slad", 0x20400000, 0xfc600000, "r,S", 2 }, +{ "slld", 0x20600000, 0xfc600000, "r,S", 2 }, +{ "sra", 0x1c000000, 0xfc600000, "r,S", 2 }, +{ "srl", 0x1c200000, 0xfc600000, "r,S", 2 }, +{ "src", 0x24000000, 0xfc600000, "r,S", 2 }, +{ "srad", 0x20000000, 0xfc600000, "r,S", 2 }, +{ "srld", 0x20200000, 0xfc600000, "r,S", 2 }, +{ "sda", 0x3c030000, 0xfc0f0000, "r,R", 2 }, +{ "sdl", 0x3c020000, 0xfc0f0000, "r,R", 2 }, +{ "sdc", 0x3c010000, 0xfc0f0000, "r,R", 2 }, +{ "sdad", 0x3c0b0000, 0xfc0f0000, "r,R", 2 }, +{ "sdld", 0x3c0a0000, 0xfc0f0000, "r,R", 2 }, + +{ "svda", 0x3c070000, 0xfc0f0000, "v,R", 2 }, +{ "svdl", 0x3c060000, 0xfc0f0000, "v,R", 2 }, +{ "svdc", 0x3c050000, 0xfc0f0000, "v,R", 2 }, +{ "svdad", 0x3c0e0000, 0xfc0f0000, "v,R", 2 }, +{ "svdld", 0x3c0d0000, 0xfc0f0000, "v,R", 2 }, + +{ "sbm", 0xac080000, 0xfc080000, "f,xOA,X", 4 }, +{ "zbm", 0xac000000, 0xfc080000, "f,xOA,X", 4 }, +{ "tbm", 0xa8080000, 0xfc080000, "f,xOA,X", 4 }, +{ "incmb", 0xa0000000, 0xfc080000, "xOA,X", 4 }, +{ "incmh", 0xa0080000, 0xfc080000, "xOA,X", 4 }, +{ "incmw", 0xa4000000, 0xfc080000, "xOA,X", 4 }, +{ "incmd", 0xa4080000, 0xfc080000, "xOA,X", 4 }, +{ "sbmd", 0x7c080000, 0xfc080000, "r,xOA,X", 4 }, +{ "zbmd", 0x7c000000, 0xfc080000, "r,xOA,X", 4 }, +{ "tbmd", 0x78080000, 0xfc080000, "r,xOA,X", 4 }, + +{ "ssm", 0x9c080000, 0xfc080000, "f,xOA,X", 4 }, +{ "zsm", 0x9c000000, 0xfc080000, "f,xOA,X", 4 }, +{ "tsm", 0x98080000, 0xfc080000, "f,xOA,X", 4 }, + +{ "admb", 0xc8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "admh", 0xc8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "admw", 0xc8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "admd", 0xc8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "adr", 0x38000000, 0xfc0f0000, "r,R", 2 }, +{ "armb", 0xe8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "armh", 0xe8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "armw", 0xe8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "armd", 0xe8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "adi", 0xf8010000, 0xfc0f0000, "r,I", 4 }, +{ "sumb", 0xcc080000, 0xfc080000, "r,xOA,X", 4 }, +{ "sumh", 0xcc000001, 0xfc080001, "r,xOA,X", 4 }, +{ "sumw", 0xcc000000, 0xfc080000, "r,xOA,X", 4 }, +{ "sumd", 0xcc000002, 0xfc080002, "r,xOA,X", 4 }, +{ "sur", 0x3c000000, 0xfc0f0000, "r,R", 2 }, +{ "sui", 0xf8020000, 0xfc0f0000, "r,I", 4 }, +{ "mpmb", 0xc0080000, 0xfc080000, "r,xOA,X", 4 }, +{ "mpmh", 0xc0000001, 0xfc080001, "r,xOA,X", 4 }, +{ "mpmw", 0xc0000000, 0xfc080000, "r,xOA,X", 4 }, +{ "mpr", 0x38020000, 0xfc0f0000, "r,R", 2 }, +{ "mprd", 0x3c0f0000, 0xfc0f0000, "r,R", 2 }, +{ "mpi", 0xf8030000, 0xfc0f0000, "r,I", 4 }, +{ "dvmb", 0xc4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "dvmh", 0xc4000001, 0xfc080001, "r,xOA,X", 4 }, +{ "dvmw", 0xc4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "dvr", 0x380a0000, 0xfc0f0000, "r,R", 2 }, +{ "dvi", 0xf8040000, 0xfc0f0000, "r,I", 4 }, +{ "exs", 0x38080000, 0xfc0f0000, "r,R", 2 }, + +{ "advv", 0x30000000, 0xfc0f0000, "v,V", 2 }, +{ "advvd", 0x30080000, 0xfc0f0000, "v,V", 2 }, +{ "adrv", 0x34000000, 0xfc0f0000, "v,R", 2 }, +{ "adrvd", 0x34080000, 0xfc0f0000, "v,R", 2 }, +{ "suvv", 0x30010000, 0xfc0f0000, "v,V", 2 }, +{ "suvvd", 0x30090000, 0xfc0f0000, "v,V", 2 }, +{ "surv", 0x34010000, 0xfc0f0000, "v,R", 2 }, +{ "survd", 0x34090000, 0xfc0f0000, "v,R", 2 }, +{ "mpvv", 0x30020000, 0xfc0f0000, "v,V", 2 }, +{ "mprv", 0x34020000, 0xfc0f0000, "v,R", 2 }, + +{ "adfw", 0xe0080000, 0xfc080000, "r,xOA,X", 4 }, +{ "adfd", 0xe0080002, 0xfc080002, "r,xOA,X", 4 }, +{ "adrfw", 0x38010000, 0xfc0f0000, "r,R", 2 }, +{ "adrfd", 0x38090000, 0xfc0f0000, "r,R", 2 }, +{ "surfw", 0xe0000000, 0xfc080000, "r,xOA,X", 4 }, +{ "surfd", 0xe0000002, 0xfc080002, "r,xOA,X", 4 }, +{ "surfw", 0x38030000, 0xfc0f0000, "r,R", 2 }, +{ "surfd", 0x380b0000, 0xfc0f0000, "r,R", 2 }, +{ "mpfw", 0xe4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "mpfd", 0xe4080002, 0xfc080002, "r,xOA,X", 4 }, +{ "mprfw", 0x38060000, 0xfc0f0000, "r,R", 2 }, +{ "mprfd", 0x380e0000, 0xfc0f0000, "r,R", 2 }, +{ "rfw", 0xe4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "rfd", 0xe4000002, 0xfc080002, "r,xOA,X", 4 }, +{ "rrfw", 0x0c0e0000, 0xfc0f0000, "r", 2 }, +{ "rrfd", 0x0c0f0000, 0xfc0f0000, "r", 2 }, + +{ "advvfw", 0x30040000, 0xfc0f0000, "v,V", 2 }, +{ "advvfd", 0x300c0000, 0xfc0f0000, "v,V", 2 }, +{ "adrvfw", 0x34040000, 0xfc0f0000, "v,R", 2 }, +{ "adrvfd", 0x340c0000, 0xfc0f0000, "v,R", 2 }, +{ "suvvfw", 0x30050000, 0xfc0f0000, "v,V", 2 }, +{ "suvvfd", 0x300d0000, 0xfc0f0000, "v,V", 2 }, +{ "survfw", 0x34050000, 0xfc0f0000, "v,R", 2 }, +{ "survfd", 0x340d0000, 0xfc0f0000, "v,R", 2 }, +{ "mpvvfw", 0x30060000, 0xfc0f0000, "v,V", 2 }, +{ "mpvvfd", 0x300e0000, 0xfc0f0000, "v,V", 2 }, +{ "mprvfw", 0x34060000, 0xfc0f0000, "v,R", 2 }, +{ "mprvfd", 0x340e0000, 0xfc0f0000, "v,R", 2 }, +{ "rvfw", 0x30070000, 0xfc0f0000, "v", 2 }, +{ "rvfd", 0x300f0000, 0xfc0f0000, "v", 2 }, + +{ "fltw", 0x38070000, 0xfc0f0000, "r,R", 2 }, +{ "fltd", 0x380f0000, 0xfc0f0000, "r,R", 2 }, +{ "fixw", 0x38050000, 0xfc0f0000, "r,R", 2 }, +{ "fixd", 0x380d0000, 0xfc0f0000, "r,R", 2 }, +{ "cfpds", 0x3c090000, 0xfc0f0000, "r,R", 2 }, + +{ "fltvw", 0x080d0000, 0xfc0f0000, "v,V", 2 }, +{ "fltvd", 0x080f0000, 0xfc0f0000, "v,V", 2 }, +{ "fixvw", 0x080c0000, 0xfc0f0000, "v,V", 2 }, +{ "fixvd", 0x080e0000, 0xfc0f0000, "v,V", 2 }, +{ "cfpvds", 0x0c0d0000, 0xfc0f0000, "v,V", 2 }, + +{ "orvrn", 0x000a0000, 0xfc0f0000, "r,V", 2 }, +{ "andvrn", 0x00080000, 0xfc0f0000, "r,V", 2 }, +{ "frsteq", 0x04090000, 0xfc0f0000, "r,V", 2 }, +{ "sigma", 0x0c080000, 0xfc0f0000, "r,V", 2 }, +{ "sigmad", 0x0c0a0000, 0xfc0f0000, "r,V", 2 }, +{ "sigmf", 0x08080000, 0xfc0f0000, "r,V", 2 }, +{ "sigmfd", 0x080a0000, 0xfc0f0000, "r,V", 2 }, +{ "prodf", 0x04080000, 0xfc0f0000, "r,V", 2 }, +{ "prodfd", 0x040a0000, 0xfc0f0000, "r,V", 2 }, +{ "maxv", 0x10080000, 0xfc0f0000, "r,V", 2 }, +{ "maxvd", 0x100a0000, 0xfc0f0000, "r,V", 2 }, +{ "minv", 0x14080000, 0xfc0f0000, "r,V", 2 }, +{ "minvd", 0x140a0000, 0xfc0f0000, "r,V", 2 }, + +{ "lpsd", 0xf0000000, 0xfc080000, "xOA,X", 4 }, +{ "ldc", 0xf0080000, 0xfc080000, "xOA,X", 4 }, +{ "spm", 0x040c0000, 0xfc0f0000, "r", 2 }, +{ "rpm", 0x040d0000, 0xfc0f0000, "r", 2 }, +{ "tritr", 0x00070000, 0xfc0f0000, "r", 2 }, +{ "trrit", 0x00060000, 0xfc0f0000, "r", 2 }, +{ "rpswt", 0x04080000, 0xfc0f0000, "r", 2 }, +{ "exr", 0xf8070000, 0xfc0f0000, "", 4 }, +{ "halt", 0x00000000, 0xfc0f0000, "", 2 }, +{ "wait", 0x00010000, 0xfc0f0000, "", 2 }, +{ "nop", 0x00020000, 0xfc0f0000, "", 2 }, +{ "eiae", 0x00030000, 0xfc0f0000, "", 2 }, +{ "efae", 0x000d0000, 0xfc0f0000, "", 2 }, +{ "diae", 0x000e0000, 0xfc0f0000, "", 2 }, +{ "dfae", 0x000f0000, 0xfc0f0000, "", 2 }, +{ "spvc", 0xf8060000, 0xfc0f0000, "r,T,N", 4 }, +{ "rdsts", 0x00090000, 0xfc0f0000, "r", 2 }, +{ "setcpu", 0x000c0000, 0xfc0f0000, "r", 2 }, +{ "cmc", 0x000b0000, 0xfc0f0000, "r", 2 }, +{ "trrcu", 0x00040000, 0xfc0f0000, "r", 2 }, +{ "attnio", 0x00050000, 0xfc0f0000, "", 2 }, +{ "fudit", 0x28080000, 0xfc0f0000, "", 2 }, +{ "break", 0x28090000, 0xfc0f0000, "", 2 }, +{ "frzss", 0x280a0000, 0xfc0f0000, "", 2 }, +{ "ripi", 0x04040000, 0xfc0f0000, "r,R", 2 }, +{ "xcp", 0x04050000, 0xfc0f0000, "r", 2 }, +{ "block", 0x04060000, 0xfc0f0000, "", 2 }, +{ "unblock", 0x04070000, 0xfc0f0000, "", 2 }, +{ "trsc", 0x08060000, 0xfc0f0000, "r,R", 2 }, +{ "tscr", 0x08070000, 0xfc0f0000, "r,R", 2 }, +{ "fq", 0x04080000, 0xfc0f0000, "r", 2 }, +{ "flupte", 0x2c080000, 0xfc0f0000, "r", 2 }, +{ "rviu", 0x040f0000, 0xfc0f0000, "", 2 }, +{ "ldel", 0x280c0000, 0xfc0f0000, "r,R", 2 }, +{ "ldu", 0x280d0000, 0xfc0f0000, "r,R", 2 }, +{ "stdecc", 0x280b0000, 0xfc0f0000, "r,R", 2 }, +{ "trpc", 0x08040000, 0xfc0f0000, "r", 2 }, +{ "tpcr", 0x08050000, 0xfc0f0000, "r", 2 }, +{ "ghalt", 0x0c050000, 0xfc0f0000, "r", 2 }, +{ "grun", 0x0c040000, 0xfc0f0000, "", 2 }, +{ "tmpr", 0x2c0a0000, 0xfc0f0000, "r,R", 2 }, +{ "trmp", 0x2c0b0000, 0xfc0f0000, "r,R", 2 }, + +{ "trrve", 0x28060000, 0xfc0f0000, "r", 2 }, +{ "trver", 0x28070000, 0xfc0f0000, "r", 2 }, +{ "trvlr", 0x280f0000, 0xfc0f0000, "r", 2 }, + +{ "linkfl", 0x18000000, 0xfc0f0000, "r,R", 2 }, +{ "linkbl", 0x18020000, 0xfc0f0000, "r,R", 2 }, +{ "linkfp", 0x18010000, 0xfc0f0000, "r,R", 2 }, +{ "linkbp", 0x18030000, 0xfc0f0000, "r,R", 2 }, +{ "linkpl", 0x18040000, 0xfc0f0000, "r,R", 2 }, +{ "ulinkl", 0x18080000, 0xfc0f0000, "r,R", 2 }, +{ "ulinkp", 0x18090000, 0xfc0f0000, "r,R", 2 }, +{ "ulinktl", 0x180a0000, 0xfc0f0000, "r,R", 2 }, +{ "ulinktp", 0x180b0000, 0xfc0f0000, "r,R", 2 }, +}; + +int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]); + +struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) / + sizeof(gld_opcodes[0]); diff --git a/include/opcode/pn.h b/include/opcode/pn.h new file mode 100644 index 00000000000..fde4764c02c --- /dev/null +++ b/include/opcode/pn.h @@ -0,0 +1,282 @@ +/* Print GOULD PN (PowerNode) instructions for GDB, the GNU debugger. + Copyright (C) 1986, 1987, 1989 Free Software Foundation, Inc. + +This file is part of GDB. + +GDB is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GDB is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GDB; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +struct gld_opcode +{ + char *name; + unsigned long opcode; + unsigned long mask; + char *args; + int length; +}; + +/* We store four bytes of opcode for all opcodes because that + is the most any of them need. The actual length of an instruction + is always at least 2 bytes, and at most four. The length of the + instruction is based on the opcode. + + The mask component is a mask saying which bits must match + particular opcode in order for an instruction to be an instance + of that opcode. + + The args component is a string containing characters + that are used to format the arguments to the instruction. */ + +/* Kinds of operands: + r Register in first field + R Register in second field + b Base register in first field + B Base register in second field + v Vector register in first field + V Vector register in first field + A Optional address register (base register) + X Optional index register + I Immediate data (16bits signed) + O Offset field (16bits signed) + h Offset field (15bits signed) + d Offset field (14bits signed) + S Shift count field + + any other characters are printed as is... +*/ + +/* The assembler requires that this array be sorted as follows: + all instances of the same mnemonic must be consecutive. + All instances of the same mnemonic with the same number of operands + must be consecutive. + */ +struct gld_opcode gld_opcodes[] = +{ +{ "abm", 0xa0080000, 0xfc080000, "f,xOA,X", 4 }, +{ "abr", 0x18080000, 0xfc0c0000, "r,f", 2 }, +{ "aci", 0xfc770000, 0xfc7f8000, "r,I", 4 }, +{ "adfd", 0xe0080002, 0xfc080002, "r,xOA,X", 4 }, +{ "adfw", 0xe0080000, 0xfc080000, "r,xOA,X", 4 }, +{ "adi", 0xc8010000, 0xfc7f0000, "r,I", 4 }, +{ "admb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "admd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "admh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "admw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "adr", 0x38000000, 0xfc0f0000, "r,R", 2 }, +{ "adrfd", 0x38090000, 0xfc0f0000, "r,R", 2 }, +{ "adrfw", 0x38010000, 0xfc0f0000, "r,R", 2 }, +{ "adrm", 0x38080000, 0xfc0f0000, "r,R", 2 }, +{ "ai", 0xfc030000, 0xfc07ffff, "I", 4 }, +{ "anmb", 0x84080000, 0xfc080000, "r,xOA,X", 4 }, +{ "anmd", 0x84000002, 0xfc080002, "r,xOA,X", 4 }, +{ "anmh", 0x84000001, 0xfc080001, "r,xOA,X", 4 }, +{ "anmw", 0x84000000, 0xfc080000, "r,xOA,X", 4 }, +{ "anr", 0x04000000, 0xfc0f0000, "r,R", 2 }, +{ "armb", 0xe8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "armd", 0xe8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "armh", 0xe8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "armw", 0xe8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bcf", 0xf0000000, 0xfc080000, "I,xOA,X", 4 }, +{ "bct", 0xec000000, 0xfc080000, "I,xOA,X", 4 }, +{ "bei", 0x00060000, 0xffff0000, "", 2 }, +{ "bft", 0xf0000000, 0xff880000, "xOA,X", 4 }, +{ "bib", 0xf4000000, 0xfc780000, "r,xOA", 4 }, +{ "bid", 0xf4600000, 0xfc780000, "r,xOA", 4 }, +{ "bih", 0xf4200000, 0xfc780000, "r,xOA", 4 }, +{ "biw", 0xf4400000, 0xfc780000, "r,xOA", 4 }, +{ "bl", 0xf8800000, 0xff880000, "xOA,X", 4 }, +{ "bsub", 0x5c080000, 0xff8f0000, "", 2 }, +{ "bsubm", 0x28080000, 0xfc080000, "", 4 }, +{ "bu", 0xec000000, 0xff880000, "xOA,X", 4 }, +{ "call", 0x28080000, 0xfc0f0000, "", 2 }, +{ "callm", 0x5c080000, 0xff880000, "", 4 }, +{ "camb", 0x90080000, 0xfc080000, "r,xOA,X", 4 }, +{ "camd", 0x90000002, 0xfc080002, "r,xOA,X", 4 }, +{ "camh", 0x90000001, 0xfc080001, "r,xOA,X", 4 }, +{ "camw", 0x90000000, 0xfc080000, "r.xOA,X", 4 }, +{ "car", 0x10000000, 0xfc0f0000, "r,R", 2 }, +{ "cd", 0xfc060000, 0xfc070000, "r,f", 4 }, +{ "cea", 0x000f0000, 0xffff0000, "", 2 }, +{ "ci", 0xc8050000, 0xfc7f0000, "r,I", 4 }, +{ "cmc", 0x040a0000, 0xfc7f0000, "r", 2 }, +{ "cmmb", 0x94080000, 0xfc080000, "r,xOA,X", 4 }, +{ "cmmd", 0x94000002, 0xfc080002, "r,xOA,X", 4 }, +{ "cmmh", 0x94000001, 0xfc080001, "r,xOA,X", 4 }, +{ "cmmw", 0x94000000, 0xfc080000, "r,xOA,X", 4 }, +{ "cmr", 0x14000000, 0xfc0f0000, "r,R", 2 }, +{ "daci", 0xfc7f0000, 0xfc7f8000, "r,I", 4 }, +{ "dae", 0x000e0000, 0xffff0000, "", 2 }, +{ "dai", 0xfc040000, 0xfc07ffff, "I", 4 }, +{ "dci", 0xfc6f0000, 0xfc7f8000, "r,I", 4 }, +{ "di", 0xfc010000, 0xfc07ffff, "I", 4 }, +{ "dvfd", 0xe4000002, 0xfc080002, "r,xOA,X", 4 }, +{ "dvfw", 0xe4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "dvi", 0xc8040000, 0xfc7f0000, "r,I", 4 }, +{ "dvmb", 0xc4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "dvmh", 0xc4000001, 0xfc080001, "r,xOA,X", 4 }, +{ "dvmw", 0xc4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "dvr", 0x380a0000, 0xfc0f0000, "r,R", 2 }, +{ "dvrfd", 0x380c0000, 0xfc0f0000, "r,R", 4 }, +{ "dvrfw", 0x38040000, 0xfc0f0000, "r,xOA,X", 4 }, +{ "eae", 0x00080000, 0xffff0000, "", 2 }, +{ "eci", 0xfc670000, 0xfc7f8080, "r,I", 4 }, +{ "ecwcs", 0xfc4f0000, 0xfc7f8000, "", 4 }, +{ "ei", 0xfc000000, 0xfc07ffff, "I", 4 }, +{ "eomb", 0x8c080000, 0xfc080000, "r,xOA,X", 4 }, +{ "eomd", 0x8c000002, 0xfc080002, "r,xOA,X", 4 }, +{ "eomh", 0x8c000001, 0xfc080001, "r,xOA,X", 4 }, +{ "eomw", 0x8c000000, 0xfc080000, "r,xOA,X", 4 }, +{ "eor", 0x0c000000, 0xfc0f0000, "r,R", 2 }, +{ "eorm", 0x0c080000, 0xfc0f0000, "r,R", 2 }, +{ "es", 0x00040000, 0xfc7f0000, "r", 2 }, +{ "exm", 0xa8000000, 0xff880000, "xOA,X", 4 }, +{ "exr", 0xc8070000, 0xfc7f0000, "r", 2 }, +{ "exrr", 0xc8070002, 0xfc7f0002, "r", 2 }, +{ "fixd", 0x380d0000, 0xfc0f0000, "r,R", 2 }, +{ "fixw", 0x38050000, 0xfc0f0000, "r,R", 2 }, +{ "fltd", 0x380f0000, 0xfc0f0000, "r,R", 2 }, +{ "fltw", 0x38070000, 0xfc0f0000, "r,R", 2 }, +{ "grio", 0xfc3f0000, 0xfc7f8000, "r,I", 4 }, +{ "halt", 0x00000000, 0xffff0000, "", 2 }, +{ "hio", 0xfc370000, 0xfc7f8000, "r,I", 4 }, +{ "jwcs", 0xfa080000, 0xff880000, "xOA,X", 4 }, +{ "la", 0x50000000, 0xfc000000, "r,xOA,X", 4 }, +{ "labr", 0x58080000, 0xfc080000, "b,xOA,X", 4 }, +{ "lb", 0xac080000, 0xfc080000, "r,xOA,X", 4 }, +{ "lcs", 0x00030000, 0xfc7f0000, "r", 2 }, +{ "ld", 0xac000002, 0xfc080002, "r,xOA,X", 4 }, +{ "lear", 0x80000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lf", 0xcc000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lfbr", 0xcc080000, 0xfc080000, "b,xOA,X", 4 }, +{ "lh", 0xac000001, 0xfc080001, "r,xOA,X", 4 }, +{ "li", 0xc8000000, 0xfc7f0000, "r,I", 4 }, +{ "lmap", 0x2c070000, 0xfc7f0000, "r", 2 }, +{ "lmb", 0xb0080000, 0xfc080000, "r,xOA,X", 4 }, +{ "lmd", 0xb0000002, 0xfc080002, "r,xOA,X", 4 }, +{ "lmh", 0xb0000001, 0xfc080001, "r,xOA,X", 4 }, +{ "lmw", 0xb0000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lnb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "lnd", 0xb4000002, 0xfc080002, "r,xOA,X", 4 }, +{ "lnh", 0xb4000001, 0xfc080001, "r,xOA,X", 4 }, +{ "lnw", 0xb4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lpsd", 0xf9800000, 0xff880000, "r,xOA,X", 4 }, +{ "lpsdcm", 0xfa800000, 0xff880000, "r,xOA,X", 4 }, +{ "lw", 0xac000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lwbr", 0x5c000000, 0xfc080000, "b,xOA,X", 4 }, +{ "mpfd", 0xe4080002, 0xfc080002, "r,xOA,X", 4 }, +{ "mpfw", 0xe4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "mpi", 0xc8030000, 0xfc7f0000, "r,I", 4 }, +{ "mpmb", 0xc0080000, 0xfc080000, "r,xOA,X", 4 }, +{ "mpmh", 0xc0000001, 0xfc080001, "r,xOA,X", 4 }, +{ "mpmw", 0xc0000000, 0xfc080000, "r,xOA,X", 4 }, +{ "mpr", 0x38020000, 0xfc0f0000, "r,R", 2 }, +{ "mprfd", 0x380e0000, 0xfc0f0000, "r,R", 2 }, +{ "mprfw", 0x38060000, 0xfc0f0000, "r,R", 2 }, +{ "nop", 0x00020000, 0xffff0000, "", 2 }, +{ "ormb", 0x88080000, 0xfc080000, "r,xOA,X", 4 }, +{ "ormd", 0x88000002, 0xfc080002, "r,xOA,X", 4 }, +{ "ormh", 0x88000001, 0xfc080001, "r,xOA,X", 4 }, +{ "ormw", 0x88000000, 0xfc080000, "r,xOA,X", 4 }, +{ "orr", 0x08000000, 0xfc0f0000, "r,R", 2 }, +{ "orrm", 0x08080000, 0xfc0f0000, "r,R", 2 }, +{ "rdsts", 0x00090000, 0xfc7f0000, "r", 2 }, +{ "return", 0x280e0000, 0xfc7f0000, "", 2 }, +{ "ri", 0xfc020000, 0xfc07ffff, "I", 4 }, +{ "rnd", 0x00050000, 0xfc7f0000, "r", 2 }, +{ "rpswt", 0x040b0000, 0xfc7f0000, "r", 2 }, +{ "rschnl", 0xfc2f0000, 0xfc7f8000, "r,I", 4 }, +{ "rsctl", 0xfc470000, 0xfc7f8000, "r,I", 4 }, +{ "rwcs", 0x000b0000, 0xfc0f0000, "r,R", 2 }, +{ "sacz", 0x10080000, 0xfc0f0000, "r,R", 2 }, +{ "sbm", 0x98080000, 0xfc080000, "f,xOA,X", 4 }, +{ "sbr", 0x18000000, 0xfc0c0000, "r,f", 4 }, +{ "sea", 0x000d0000, 0xffff0000, "", 2 }, +{ "setcpu", 0x2c090000, 0xfc7f0000, "r", 2 }, +{ "sio", 0xfc170000, 0xfc7f8000, "r,I", 4 }, +{ "sipu", 0x000a0000, 0xffff0000, "", 2 }, +{ "sla", 0x1c400000, 0xfc600000, "r,S", 2 }, +{ "slad", 0x20400000, 0xfc600000, "r,S", 2 }, +{ "slc", 0x24400000, 0xfc600000, "r,S", 2 }, +{ "sll", 0x1c600000, 0xfc600000, "r,S", 2 }, +{ "slld", 0x20600000, 0xfc600000, "r,S", 2 }, +{ "smc", 0x04070000, 0xfc070000, "", 2 }, +{ "sra", 0x1c000000, 0xfc600000, "r,S", 2 }, +{ "srad", 0x20000000, 0xfc600000, "r,S", 2 }, +{ "src", 0x24000000, 0xfc600000, "r,S", 2 }, +{ "srl", 0x1c200000, 0xfc600000, "r,S", 2 }, +{ "srld", 0x20200000, 0xfc600000, "r,S", 2 }, +{ "stb", 0xd4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "std", 0xd4000002, 0xfc080002, "r,xOA,X", 4 }, +{ "stf", 0xdc000000, 0xfc080000, "r,xOA,X", 4 }, +{ "stfbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, +{ "sth", 0xd4000001, 0xfc080001, "r,xOA,X", 4 }, +{ "stmb", 0xd8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "stmd", 0xd8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "stmh", 0xd8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "stmw", 0xd8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "stpio", 0xfc270000, 0xfc7f8000, "r,I", 4 }, +{ "stw", 0xd4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "stwbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, +{ "suabr", 0x58000000, 0xfc080000, "b,xOA,X", 4 }, +{ "sufd", 0xe0000002, 0xfc080002, "r,xOA,X", 4 }, +{ "sufw", 0xe0000000, 0xfc080000, "r,xOA,X", 4 }, +{ "sui", 0xc8020000, 0xfc7f0000, "r,I", 4 }, +{ "sumb", 0xbc080000, 0xfc080000, "r,xOA,X", 4 }, +{ "sumd", 0xbc000002, 0xfc080002, "r,xOA,X", 4 }, +{ "sumh", 0xbc000001, 0xfc080001, "r,xOA,X", 4 }, +{ "sumw", 0xbc000000, 0xfc080000, "r,xOA,X", 4 }, +{ "sur", 0x3c000000, 0xfc0f0000, "r,R", 2 }, +{ "surfd", 0x380b0000, 0xfc0f0000, "r,xOA,X", 4 }, +{ "surfw", 0x38030000, 0xfc0f0000, "r,R", 2 }, +{ "surm", 0x3c080000, 0xfc0f0000, "r,R", 2 }, +{ "svc", 0xc8060000, 0xffff0000, "", 4 }, +{ "tbm", 0xa4080000, 0xfc080000, "f,xOA,X", 4 }, +{ "tbr", 0x180c0000, 0xfc0c0000, "r,f", 2 }, +{ "tbrr", 0x2c020000, 0xfc0f0000, "r,B", 2 }, +{ "tccr", 0x28040000, 0xfc7f0000, "", 2 }, +{ "td", 0xfc050000, 0xfc070000, "r,f", 4 }, +{ "tio", 0xfc1f0000, 0xfc7f8000, "r,I", 4 }, +{ "tmapr", 0x2c0a0000, 0xfc0f0000, "r,R", 2 }, +{ "tpcbr", 0x280c0000, 0xfc7f0000, "r", 2 }, +{ "trbr", 0x2c010000, 0xfc0f0000, "b,R", 2 }, +{ "trc", 0x2c030000, 0xfc0f0000, "r,R", 2 }, +{ "trcc", 0x28050000, 0xfc7f0000, "", 2 }, +{ "trcm", 0x2c0b0000, 0xfc0f0000, "r,R", 2 }, +{ "trn", 0x2c040000, 0xfc0f0000, "r,R", 2 }, +{ "trnm", 0x2c0c0000, 0xfc0f0000, "r,R", 2 }, +{ "trr", 0x2c000000, 0xfc0f0000, "r,R", 2 }, +{ "trrm", 0x2c080000, 0xfc0f0000, "r,R", 2 }, +{ "trsc", 0x2c0e0000, 0xfc0f0000, "r,R", 2 }, +{ "trsw", 0x28000000, 0xfc7f0000, "r", 2 }, +{ "tscr", 0x2c0f0000, 0xfc0f0000, "r,R", 2 }, +{ "uei", 0x00070000, 0xffff0000, "", 2 }, +{ "wait", 0x00010000, 0xffff0000, "", 2 }, +{ "wcwcs", 0xfc5f0000, 0xfc7f8000, "", 4 }, +{ "wwcs", 0x000c0000, 0xfc0f0000, "r,R", 2 }, +{ "xcbr", 0x28020000, 0xfc0f0000, "b,B", 2 }, +{ "xcr", 0x2c050000, 0xfc0f0000, "r,R", 2 }, +{ "xcrm", 0x2c0d0000, 0xfc0f0000, "r,R", 2 }, +{ "zbm", 0x9c080000, 0xfc080000, "f,xOA,X", 4 }, +{ "zbr", 0x18040000, 0xfc0c0000, "r,f", 2 }, +{ "zmb", 0xf8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "zmd", 0xf8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "zmh", 0xf8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "zmw", 0xf8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "zr", 0x0c000000, 0xfc0f0000, "r", 2 }, +}; + +int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]); + +struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) / + sizeof(gld_opcodes[0]); diff --git a/include/opcode/pyr.h b/include/opcode/pyr.h new file mode 100644 index 00000000000..06632b8d919 --- /dev/null +++ b/include/opcode/pyr.h @@ -0,0 +1,287 @@ +/* pyramid.opcode.h -- gdb initial attempt. */ + +/* pyramid opcode table: wot to do with this + particular opcode */ + +struct pyr_datum +{ + char nargs; + char * args; /* how to compile said opcode */ + unsigned long mask; /* Bit vector: which operand modes are valid + for this opcode */ + unsigned char code; /* op-code (always 6(?) bits */ +}; + +typedef struct pyr_insn_format { + unsigned int mode :4; + unsigned int operator :8; + unsigned int index_scale :2; + unsigned int index_reg :6; + unsigned int operand_1 :6; + unsigned int operand_2:6; +} pyr_insn_format; + + +/* We store four bytes of opcode for all opcodes. + Pyramid is sufficiently RISCy that: + - insns are always an integral number of words; + - the length of any insn can be told from the first word of + the insn. (ie, if there are zero, one, or two words of + immediate operand/offset). + + + The args component is a string containing two characters for each + operand of the instruction. The first specifies the kind of operand; + the second, the place it is stored. */ + +/* Kinds of operands: + mask assembler syntax description + 0x0001: movw Rn,Rn register to register + 0x0002: movw K,Rn quick immediate to register + 0x0004: movw I,Rn long immediate to register + 0x0008: movw (Rn),Rn register indirect to register + movw (Rn)[x],Rn register indirect to register + 0x0010: movw I(Rn),Rn offset register indirect to register + movw I(Rn)[x],Rn offset register indirect, indexed, to register + + 0x0020: movw Rn,(Rn) register to register indirect + 0x0040: movw K,(Rn) quick immediate to register indirect + 0x0080: movw I,(Rn) long immediate to register indirect + 0x0100: movw (Rn),(Rn) register indirect to-register indirect + 0x0100: movw (Rn),(Rn) register indirect to-register indirect + 0x0200: movw I(Rn),(Rn) register indirect+offset to register indirect + 0x0200: movw I(Rn),(Rn) register indirect+offset to register indirect + + 0x0400: movw Rn,I(Rn) register to register indirect+offset + 0x0800: movw K,I(Rn) quick immediate to register indirect+offset + 0x1000: movw I,I(Rn) long immediate to register indirect+offset + 0x1000: movw (Rn),I(Rn) register indirect to-register indirect+offset + 0x1000: movw I(Rn),I(Rn) register indirect+offset to register indirect + +offset + 0x0000: (irregular) ??? + + + Each insn has a four-bit field encoding the type(s) of its operands. +*/ + +/* Some common combinations + */ + +/* the first 5,(0x1|0x2|0x4|0x8|0x10) ie (1|2|4|8|16), ie ( 32 -1)*/ +#define GEN_TO_REG (31) + +#define UNKNOWN ((unsigned long)-1) +#define ANY (GEN_TO_REG | (GEN_TO_REG << 5) | (GEN_TO_REG << 15)) + +#define CONVERT (1|8|0x10|0x20|0x200) + +#define K_TO_REG (2) +#define I_TO_REG (4) +#define NOTK_TO_REG (GEN_TO_REG & ~K_TO_REG) +#define NOTI_TO_REG (GEN_TO_REG & ~I_TO_REG) + +/* The assembler requires that this array be sorted as follows: + all instances of the same mnemonic must be consecutive. + All instances of the same mnemonic with the same number of operands + must be consecutive. + */ + +struct pyr_opcode /* pyr opcode text */ +{ + char * name; /* opcode name: lowercase string [key] */ + struct pyr_datum datum; /* rest of opcode table [datum] */ +}; + +#define pyr_how args +#define pyr_nargs nargs +#define pyr_mask mask +#define pyr_name name + +struct pyr_opcode pyr_opcodes[] = +{ + {"movb", { 2, "", UNKNOWN, 0x11}, }, + {"movh", { 2, "", UNKNOWN, 0x12} }, + {"movw", { 2, "", ANY, 0x10} }, + {"movl", { 2, "", ANY, 0x13} }, + {"mnegw", { 2, "", (0x1|0x8|0x10), 0x14} }, + {"mnegf", { 2, "", 0x1, 0x15} }, + {"mnegd", { 2, "", 0x1, 0x16} }, + {"mcomw", { 2, "", (0x1|0x8|0x10), 0x17} }, + {"mabsw", { 2, "", (0x1|0x8|0x10), 0x18} }, + {"mabsf", { 2, "", 0x1, 0x19} }, + {"mabsd", { 2, "", 0x1, 0x1a} }, + {"mtstw", { 2, "", (0x1|0x8|0x10), 0x1c} }, + {"mtstf", { 2, "", 0x1, 0x1d} }, + {"mtstd", { 2, "", 0x1, 0x1e} }, + {"mova", { 2, "", 0x8|0x10, 0x1f} }, + {"movzbw", { 2, "", (0x1|0x8|0x10), 0x20} }, + {"movzhw", { 2, "", (0x1|0x8|0x10), 0x21} }, + /* 2 insns out of order here */ + {"movbl", { 2, "", 1, 0x4f} }, + {"filbl", { 2, "", 1, 0x4e} }, + + {"cvtbw", { 2, "", CONVERT, 0x22} }, + {"cvthw", { 2, "", CONVERT, 0x23} }, + {"cvtwb", { 2, "", CONVERT, 0x24} }, + {"cvtwh", { 2, "", CONVERT, 0x25} }, + {"cvtwf", { 2, "", CONVERT, 0x26} }, + {"cvtwd", { 2, "", CONVERT, 0x27} }, + {"cvtfw", { 2, "", CONVERT, 0x28} }, + {"cvtfd", { 2, "", CONVERT, 0x29} }, + {"cvtdw", { 2, "", CONVERT, 0x2a} }, + {"cvtdf", { 2, "", CONVERT, 0x2b} }, + + {"addw", { 2, "", GEN_TO_REG, 0x40} }, + {"addwc", { 2, "", GEN_TO_REG, 0x41} }, + {"subw", { 2, "", GEN_TO_REG, 0x42} }, + {"subwb", { 2, "", GEN_TO_REG, 0x43} }, + {"rsubw", { 2, "", GEN_TO_REG, 0x44} }, + {"mulw", { 2, "", GEN_TO_REG, 0x45} }, + {"emul", { 2, "", GEN_TO_REG, 0x47} }, + {"umulw", { 2, "", GEN_TO_REG, 0x46} }, + {"divw", { 2, "", GEN_TO_REG, 0x48} }, + {"ediv", { 2, "", GEN_TO_REG, 0x4a} }, + {"rdivw", { 2, "", GEN_TO_REG, 0x4b} }, + {"udivw", { 2, "", GEN_TO_REG, 0x49} }, + {"modw", { 2, "", GEN_TO_REG, 0x4c} }, + {"umodw", { 2, "", GEN_TO_REG, 0x4d} }, + + + {"addf", { 2, "", 1, 0x50} }, + {"addd", { 2, "", 1, 0x51} }, + {"subf", { 2, "", 1, 0x52} }, + {"subd", { 2, "", 1, 0x53} }, + {"mulf", { 2, "", 1, 0x56} }, + {"muld", { 2, "", 1, 0x57} }, + {"divf", { 2, "", 1, 0x58} }, + {"divd", { 2, "", 1, 0x59} }, + + + {"cmpb", { 2, "", UNKNOWN, 0x61} }, + {"cmph", { 2, "", UNKNOWN, 0x62} }, + {"cmpw", { 2, "", UNKNOWN, 0x60} }, + {"ucmpb", { 2, "", UNKNOWN, 0x66} }, + /* WHY no "ucmph"??? */ + {"ucmpw", { 2, "", UNKNOWN, 0x65} }, + {"xchw", { 2, "", UNKNOWN, 0x0f} }, + + + {"andw", { 2, "", GEN_TO_REG, 0x30} }, + {"orw", { 2, "", GEN_TO_REG, 0x31} }, + {"xorw", { 2, "", GEN_TO_REG, 0x32} }, + {"bicw", { 2, "", GEN_TO_REG, 0x33} }, + {"lshlw", { 2, "", GEN_TO_REG, 0x38} }, + {"ashlw", { 2, "", GEN_TO_REG, 0x3a} }, + {"ashll", { 2, "", GEN_TO_REG, 0x3c} }, + {"ashrw", { 2, "", GEN_TO_REG, 0x3b} }, + {"ashrl", { 2, "", GEN_TO_REG, 0x3d} }, + {"rotlw", { 2, "", GEN_TO_REG, 0x3e} }, + {"rotrw", { 2, "", GEN_TO_REG, 0x3f} }, + + /* push and pop insns are "going away next release". */ + {"pushw", { 2, "", GEN_TO_REG, 0x0c} }, + {"popw", { 2, "", (0x1|0x8|0x10), 0x0d} }, + {"pusha", { 2, "", (0x8|0x10), 0x0e} }, + + {"bitsw", { 2, "", UNKNOWN, 0x35} }, + {"bitcw", { 2, "", UNKNOWN, 0x36} }, + /* some kind of ibra/dbra insns??*/ + {"icmpw", { 2, "", UNKNOWN, 0x67} }, + {"dcmpw", { 2, "", (1|4|0x20|0x80|0x400|0x1000), 0x69} },/*FIXME*/ + {"acmpw", { 2, "", 1, 0x6b} }, + + /* Call is written as a 1-op insn, but is always (dis)assembled as a 2-op + insn with a 2nd op of tr14. The assembler will have to grok this. */ + {"call", { 2, "", GEN_TO_REG, 0x04} }, + {"call", { 1, "", GEN_TO_REG, 0x04} }, + + {"callk", { 1, "", UNKNOWN, 0x06} },/* system call?*/ + /* Ret is usually written as a 0-op insn, but gets disassembled as a + 1-op insn. The operand is always tr15. */ + {"ret", { 0, "", UNKNOWN, 0x09} }, + {"ret", { 1, "", UNKNOWN, 0x09} }, + {"adsf", { 2, "", (1|2|4), 0x08} }, + {"retd", { 2, "", UNKNOWN, 0x0a} }, + {"btc", { 2, "", UNKNOWN, 0x01} }, + {"bfc", { 2, "", UNKNOWN, 0x02} }, + /* Careful: halt is 0x00000000. Jump must have some other (mode?)bit set?? */ + {"jump", { 1, "", UNKNOWN, 0x00} }, + {"btp", { 2, "", UNKNOWN, 0xf00} }, + /* read control-stack pointer is another 1-or-2 operand insn. */ + {"rcsp", { 2, "", UNKNOWN, 0x01f} }, + {"rcsp", { 1, "", UNKNOWN, 0x01f} } +}; + +/* end: pyramid.opcode.h */ +/* One day I will have to take the time to find out what operands + are valid for these insns, and guess at what they mean. + + I can't imagine what the "I???" insns (iglob, etc) do. + + the arithmetic-sounding insns ending in "p" sound awfully like BCD + arithmetic insns: + dshlp -> Decimal SHift Left Packed + dshrp -> Decimal SHift Right Packed + and cvtlp would be convert long to packed. + I have no idea how the operands are interpreted; but having them be + a long register with (address, length) of an in-memory packed BCD operand + would not be surprising. + They are unlikely to be a packed bcd string: 64 bits of long give + is only 15 digits+sign, which isn't enough for COBOL. + */ +#if 0 + {"wcsp", { 2, "", UNKNOWN, 0x00} }, /*write csp?*/ + /* The OSx Operating System Porting Guide claims SSL does things + with tr12 (a register reserved to it) to do with static block-structure + references. SSL=Set Static Link? It's "Going away next release". */ + {"ssl", { 2, "", UNKNOWN, 0x00} }, + {"ccmps", { 2, "", UNKNOWN, 0x00} }, + {"lcd", { 2, "", UNKNOWN, 0x00} }, + {"uemul", { 2, "", UNKNOWN, 0x00} }, /*unsigned emul*/ + {"srf", { 2, "", UNKNOWN, 0x00} }, /*Gidget time???*/ + {"mnegp", { 2, "", UNKNOWN, 0x00} }, /move-neg phys?*/ + {"ldp", { 2, "", UNKNOWN, 0x00} }, /*load phys?*/ + {"ldti", { 2, "", UNKNOWN, 0x00} }, + {"ldb", { 2, "", UNKNOWN, 0x00} }, + {"stp", { 2, "", UNKNOWN, 0x00} }, + {"stti", { 2, "", UNKNOWN, 0x00} }, + {"stb", { 2, "", UNKNOWN, 0x00} }, + {"stu", { 2, "", UNKNOWN, 0x00} }, + {"addp", { 2, "", UNKNOWN, 0x00} }, + {"subp", { 2, "", UNKNOWN, 0x00} }, + {"mulp", { 2, "", UNKNOWN, 0x00} }, + {"divp", { 2, "", UNKNOWN, 0x00} }, + {"dshlp", { 2, "", UNKNOWN, 0x00} }, /* dec shl packed? */ + {"dshrp", { 2, "", UNKNOWN, 0x00} }, /* dec shr packed? */ + {"movs", { 2, "", UNKNOWN, 0x00} }, /*move (string?)?*/ + {"cmpp", { 2, "", UNKNOWN, 0x00} }, /* cmp phys?*/ + {"cmps", { 2, "", UNKNOWN, 0x00} }, /* cmp (string?)?*/ + {"cvtlp", { 2, "", UNKNOWN, 0x00} }, /* cvt long to p??*/ + {"cvtpl", { 2, "", UNKNOWN, 0x00} }, /* cvt p to l??*/ + {"dintr", { 2, "", UNKNOWN, 0x00} }, /* ?? intr ?*/ + {"rphysw", { 2, "", UNKNOWN, 0x00} }, /* read phys word?*/ + {"wphysw", { 2, "", UNKNOWN, 0x00} }, /* write phys word?*/ + {"cmovs", { 2, "", UNKNOWN, 0x00} }, + {"rsubw", { 2, "", UNKNOWN, 0x00} }, + {"bicpsw", { 2, "", UNKNOWN, 0x00} }, /* clr bit in psw? */ + {"bispsw", { 2, "", UNKNOWN, 0x00} }, /* set bit in psw? */ + {"eio", { 2, "", UNKNOWN, 0x00} }, /* ?? ?io ? */ + {"callp", { 2, "", UNKNOWN, 0x00} }, /* call phys?*/ + {"callr", { 2, "", UNKNOWN, 0x00} }, + {"lpcxt", { 2, "", UNKNOWN, 0x00} }, /*load proc context*/ + {"rei", { 2, "", UNKNOWN, 0x00} }, /*ret from intrpt*/ + {"rport", { 2, "", UNKNOWN, 0x00} }, /*read-port?*/ + {"rtod", { 2, "", UNKNOWN, 0x00} }, /*read-time-of-day?*/ + {"ssi", { 2, "", UNKNOWN, 0x00} }, + {"vtpa", { 2, "", UNKNOWN, 0x00} }, /*virt-to-phys-addr?*/ + {"wicl", { 2, "", UNKNOWN, 0x00} }, /* write icl ? */ + {"wport", { 2, "", UNKNOWN, 0x00} }, /*write-port?*/ + {"wtod", { 2, "", UNKNOWN, 0x00} }, /*write-time-of-day?*/ + {"flic", { 2, "", UNKNOWN, 0x00} }, + {"iglob", { 2, "", UNKNOWN, 0x00} }, /* I global? */ + {"iphys", { 2, "", UNKNOWN, 0x00} }, /* I physical? */ + {"ipid", { 2, "", UNKNOWN, 0x00} }, /* I pid? */ + {"ivect", { 2, "", UNKNOWN, 0x00} }, /* I vector? */ + {"lamst", { 2, "", UNKNOWN, 0x00} }, + {"tio", { 2, "", UNKNOWN, 0x00} }, +#endif diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h new file mode 100644 index 00000000000..e9f7d6b0b6d --- /dev/null +++ b/include/opcode/sparc.h @@ -0,0 +1,1843 @@ +/* to sanitize this file, grep -v v9 < sparc-opcode.h > clean-sparc-opcode.h */ + +/* Table of opcodes for the sparc. + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + +This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. + +GAS/GDB is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GAS/GDB is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GAS or GDB; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + /* FIXME-someday: perhaps the ,a's and such should be embedded in the + instruction's name rather than the args. This would make gas faster, pinsn + slower, but would mess up some macros a bit. xoxorich. */ + +#if !defined(__STDC__) && !defined(const) +#define const +#endif + +/* + * Structure of an opcode table entry. + */ +enum sparc_architecture { + v6 = 0, + v7, + cypress, + v8, + v9, +}; + +static const char *architecture_pname[] = { + "v6", + "v7", + "cypress", + "v8", + "v9", + NULL, +}; + +struct sparc_opcode { + const char *name; + unsigned long match; /* Bits that must be set. */ + unsigned long lose; /* Bits that must not be set. */ + const char *args; + /* This was called "delayed" in versions before the flags. */ + char flags; + enum sparc_architecture architecture; +}; + +#define F_DELAYED 1 /* Delayed branch */ +#define F_ALIAS 2 /* Alias for a "real" instruction */ + +/* + +All sparc opcodes are 32 bits, except for the `set' instruction (really a +macro), which is 64 bits. It is handled as a special case. + +The match component is a mask saying which bits must match a particular +opcode in order for an instruction to be an instance of that opcode. + +The args component is a string containing one character for each operand of the +instruction. + +Kinds of operands: + # Number used by optimizer. It is ignored. + 1 rs1 register. + 2 rs2 register. + d rd register. + e frs1 floating point register. + v frs1 floating point register (double/even). + V frs1 floating point register (quad/multiple of 4). + f frs2 floating point register. + B frs2 floating point register (double/even). + R frs2 floating point register (quad/multiple of 4). + j frs3 floating point register. (v9) + u frs3 floating point register. (double/even) (v9) + U frs3 floating point register. (quad/multiple of 4) (v9) + g frsd floating point register. + H frsd floating point register (double/even). + J frsd floating point register (quad/multiple of 4). + b crs1 coprocessor register + c crs2 coprocessor register + D crsd coprocessor register + m alternate space register (asr) in rd + M alternate space register (asr) in rs1 + h 22 high bits. + I 11 bit Immediate. (v9) + i 13 bit Immediate. + k 2+14 bit PC relative immediate. (v9) + G 19 bit PC relative immediate. (v9) + l 22 bit PC relative immediate. + L 30 bit PC relative immediate. + a Annul. The annul bit is set. + A Alternate address space. Stored as 8 bits. + C Coprocessor state register. + F floating point state register. + p Processor state register. + N Branch predict clear ",pn" (v9) + T Branch predict set ",pt" (v9) + z icc. (v9) + Z xcc. (v9) + q Floating point queue. + r Single register that is both rs1 and rsd. + Q Coprocessor queue. + S Special case. + t Trap base register. + w Window invalid mask register. + y Y register. + Y %amr (v9?) + P %pc. (v9) + E %modes. (v9) + W %tick. (v9) + 6 fcc0. (v9) + 7 fcc1. (v9) + 8 fcc2. (v9) + 9 fcc3. (v9) + +The following chars are unused: (note: ,[] are used as punctuation) +[nosxOX3450] + +*/ + +/* The order of the opcodes in this table is significant: + + * The assembler requires that all instances of the same mnemonic must + be consecutive. If they aren't, the assembler will bomb at runtime. + + * The disassembler should not care about the order of the opcodes. + +*/ + +#define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */ +#define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */ +#define OP(x) (((x)&0x3) << 30) /* op field of all insns */ +#define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */ +#define OPF_LOW(x) OPF((x)&0xf) /* v9 */ +#define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */ +#define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */ +#define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */ +#define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */ +#define F1(x) (OP(x)) +#define DISP30(x) ((x)&0x3fffffff) +#define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */ +#define RS2(x) ((x)&0x1f) /* rs2 field */ +#define SIMM13(x) ((x)&0x1fff) /* simm13 field */ +#define RD(x) (((x)&0x1f) << 25) /* destination register field */ +#define RS1(x) (((x)&0x1f) << 14) /* rs1 field */ +#define ASI_RS2(x) (SIMM13(x)) + +#define ANNUL (1<<29) +#define BPRED (1<<21) /* v9 */ +#define IMMED F3I(1) +#define RD_G0 RD(~0) +#define RS1_G0 RS1(~0) +#define RS2_G0 RS2(~0) + +#define COND(x) (((x)&0xf)<<25) +#define MCOND(x) (((x)>>11)&(0xf<<14)) /* v9 */ + +#define CONDA (COND(0x8)) +#define CONDCC (COND(0xd)) +#define CONDCS (COND(0x5)) +#define CONDE (COND(0x1)) +#define CONDG (COND(0xa)) +#define CONDGE (COND(0xb)) +#define CONDGU (COND(0xc)) +#define CONDL (COND(0x3)) +#define CONDLE (COND(0x2)) +#define CONDLEU (COND(0x4)) +#define CONDN (COND(0x0)) +#define CONDNE (COND(0x9)) +#define CONDNEG (COND(0x6)) +#define CONDPOS (COND(0xe)) +#define CONDVC (COND(0xf)) +#define CONDVS (COND(0x7)) + +#define CONDNZ CONDNE +#define CONDZ CONDE +#define CONDGEU CONDCC +#define CONDLU CONDCS + +#define FCONDA (COND(0x8)) +#define FCONDE (COND(0x9)) +#define FCONDG (COND(0x6)) +#define FCONDGE (COND(0xb)) +#define FCONDL (COND(0x4)) +#define FCONDLE (COND(0xd)) +#define FCONDLG (COND(0x2)) +#define FCONDN (COND(0x0)) +#define FCONDNE (COND(0x1)) +#define FCONDO (COND(0xf)) +#define FCONDU (COND(0x7)) +#define FCONDUE (COND(0xa)) +#define FCONDUG (COND(0x5)) +#define FCONDUGE (COND(0xc)) +#define FCONDUL (COND(0x3)) +#define FCONDULE (COND(0xe)) + +#define FCONDNZ FCONDNE +#define FCONDZ FCONDE + +#define ICC (0) /* v9 */ +#define XCC (1<<11) /* v9 */ +#define FCC(x) (((x)&0x3)<<11) /* v9 */ +#define FBFCC(x) (((x)&0x3)<<19) /* v9 */ + +static struct sparc_opcode sparc_opcodes[] = { + +{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, v6 }, +{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, v6 }, /* ld [rs1+%g0],d */ +{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, v6 }, +{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, v6 }, +{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, v6 }, +{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ld [rs1+0],d */ +{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, v6 }, +{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, v6 }, /* ld [rs1+%g0],d */ +{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, v6 }, +{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, v6 }, +{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, v6 }, +{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, v6 }, /* ld [rs1+0],d */ +{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0), "[1+2],F", 0, v6 }, +{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0, "[1],F", 0, v6 }, /* ld [rs1+%g0],d */ +{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1), "[1+i],F", 0, v6 }, +{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1), "[i+1],F", 0, v6 }, +{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0, "[i],F", 0, v6 }, +{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0), "[1],F", 0, v6 }, /* ld [rs1+0],d */ +{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, v6 }, +{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, v6 }, /* ld [rs1+%g0],d */ +{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, v6 }, +{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, v6 }, +{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, v6 }, +{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, v6 }, /* ld [rs1+0],d */ +{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, v6 }, +{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, v6 }, /* ld [rs1+%g0],d */ +{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, v6 }, +{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, v6 }, +{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, v6 }, +{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, v6 }, /* ld [rs1+0],d */ + + /* FIXME-v9: combine ld, lduw, & ldw in macros. */ +{ "ldw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, v9 }, /* ldw === ld */ +{ "ldw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, v9 }, /* ld [rs1+%g0],d */ +{ "ldw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, v9 }, +{ "ldw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, v9 }, +{ "ldw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, v9 }, +{ "ldw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, v9 }, /* ld [rs1+0],d */ +{ "ldw", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", F_ALIAS, v9 }, +{ "ldw", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", F_ALIAS, v9 }, /* ld [rs1+%g0],d */ +{ "ldw", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", F_ALIAS, v9 }, +{ "ldw", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", F_ALIAS, v9 }, +{ "ldw", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", F_ALIAS, v9 }, +{ "ldw", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", F_ALIAS, v9 }, /* ld [rs1+0],d */ +{ "ldw", F3(3, 0x21, 0), F3(~3, ~0x21, ~0), "[1+2],F", F_ALIAS, v9 }, +{ "ldw", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0, "[1],F", F_ALIAS, v9 }, /* ld [rs1+%g0],d */ +{ "ldw", F3(3, 0x21, 1), F3(~3, ~0x21, ~1), "[1+i],F", F_ALIAS, v9 }, +{ "ldw", F3(3, 0x21, 1), F3(~3, ~0x21, ~1), "[i+1],F", F_ALIAS, v9 }, +{ "ldw", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0, "[i],F", F_ALIAS, v9 }, +{ "ldw", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0), "[1],F", F_ALIAS, v9 }, /* ld [rs1+0],d */ +{ "ldw", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", F_ALIAS, v9 }, +{ "ldw", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", F_ALIAS, v9 }, /* ld [rs1+%g0],d */ +{ "ldw", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", F_ALIAS, v9 }, +{ "ldw", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", F_ALIAS, v9 }, +{ "ldw", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", F_ALIAS, v9 }, +{ "ldw", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", F_ALIAS, v9 }, /* ld [rs1+0],d */ +{ "ldw", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", F_ALIAS, v9 }, +{ "ldw", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", F_ALIAS, v9 }, /* ld [rs1+%g0],d */ +{ "ldw", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", F_ALIAS, v9 }, +{ "ldw", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", F_ALIAS, v9 }, +{ "ldw", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", F_ALIAS, v9 }, +{ "ldw", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", F_ALIAS, v9 }, /* ld [rs1+0],d */ + +{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, v9 }, /* lduw === ld */ +{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, v9 }, /* ld [rs1+%g0],d */ +{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, v9 }, /* ld [rs1+0],d */ +{ "lduw", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", F_ALIAS, v9 }, /* ld [rs1+%g0],d */ +{ "lduw", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", F_ALIAS, v9 }, /* ld [rs1+0],d */ +{ "lduw", F3(3, 0x21, 0), F3(~3, ~0x21, ~0), "[1+2],F", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0, "[1],F", F_ALIAS, v9 }, /* ld [rs1+%g0],d */ +{ "lduw", F3(3, 0x21, 1), F3(~3, ~0x21, ~1), "[1+i],F", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x21, 1), F3(~3, ~0x21, ~1), "[i+1],F", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0, "[i],F", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0), "[1],F", F_ALIAS, v9 }, /* ld [rs1+0],d */ +{ "lduw", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", F_ALIAS, v9 }, /* ld [rs1+%g0],d */ +{ "lduw", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", F_ALIAS, v9 }, /* ld [rs1+0],d */ +{ "lduw", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", F_ALIAS, v9 }, /* ld [rs1+%g0],d */ +{ "lduw", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", F_ALIAS, v9 }, /* ld [rs1+0],d */ + +{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, v6 }, +{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */ + +{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, v6 }, +{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldd [rs1+%g0],d */ +{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, v6 }, +{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, v6 }, +{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, v6 }, +{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldd [rs1+0],d */ +{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],g", 0, v6 }, +{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],g", 0, v6 }, /* ldd [rs1+%g0],d */ +{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],g", 0, v6 }, +{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],g", 0, v6 }, +{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],g", 0, v6 }, +{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],g", 0, v6 }, /* ldd [rs1+0],d */ +{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, v6 }, +{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, v6 }, /* ldd [rs1+%g0],d */ +{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, v6 }, +{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, v6 }, +{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, v6 }, +{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, v6 }, /* ldd [rs1+0],d */ +{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, v6 }, +{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */ +{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, v6 }, +{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, v6 }, +{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, v6 }, +{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsb [rs1+0],d */ +{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */ +{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, v6 }, +{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, v6 }, +{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, v6 }, +{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, v6 }, +{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsh [rs1+0],d */ +{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, v6 }, +{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */ +{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, v6 }, +{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, v6 }, +{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, v6 }, +{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, v9 }, +{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldsw [rs1+%g0],d */ +{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, v9 }, +{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, v9 }, +{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, v9 }, +{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldsw [rs1+0],d */ +{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, v6 }, +{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldub [rs1+%g0],d */ +{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, v6 }, +{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, v6 }, +{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, v6 }, +{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldub [rs1+0],d */ +{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, v6 }, +{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* lduh [rs1+%g0],d */ +{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, v6 }, +{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, v6 }, +{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, v6 }, +{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* lduh [rs1+0],d */ + +{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, v9 }, +{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldx [rs1+%g0],d */ +{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, v9 }, +{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, v9 }, +{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, v9 }, +{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldx [rs1+0],d */ +{ "ldx", F3(3, 0x29, 0), F3(~3, ~0x29, ~0), "[1+2],F", 0, v9 }, +{ "ldx", F3(3, 0x29, 0), F3(~3, ~0x29, ~0)|RS2_G0, "[1],F", 0, v9 }, /* ld [rs1+%g0],d */ +{ "ldx", F3(3, 0x29, 1), F3(~3, ~0x29, ~1), "[1+i],F", 0, v9 }, +{ "ldx", F3(3, 0x29, 1), F3(~3, ~0x29, ~1), "[i+1],F", 0, v9 }, +{ "ldx", F3(3, 0x29, 1), F3(~3, ~0x29, ~1)|RS1_G0, "[i],F", 0, v9 }, +{ "ldx", F3(3, 0x29, 1), F3(~3, ~0x29, ~1)|SIMM13(~0), "[1],F", 0, v9 }, /* ld [rs1+0],d */ + +{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, v6 }, +{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldda [rs1+%g0],d */ +{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, v6 }, +{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsba [rs1+%g0],d */ +{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, v6 }, +{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsha [rs1+%g0],d */ +{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, v6 }, +{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldstuba [rs1+%g0],d */ +{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, v9 }, /* lduwa === lda */ +{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ +{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, v6 }, +{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduba [rs1+%g0],d */ +{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, v6 }, +{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduha [rs1+%g0],d */ +{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS, v9 }, /* lduwa === lda */ +{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, v9 }, /* lda [rs1+%g0],d */ +{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, v9 }, /* lduwa === lda */ +{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ + +{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, +{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* st d,[rs1+%g0] */ +{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, v6 }, +{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, v6 }, +{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", 0, v6 }, +{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* st d,[rs1+0] */ +{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, v6 }, +{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, v6 }, /* st d[rs1+%g0] */ +{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, v6 }, +{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, v6 }, +{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", 0, v6 }, +{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, v6 }, /* st d,[rs1+0] */ +{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, v6 }, +{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, v6 }, /* st d,[rs1+%g0] */ +{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, v6 }, +{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, v6 }, +{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", 0, v6 }, +{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, v6 }, /* st d,[rs1+0] */ +{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, v6 }, +{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, v6 }, /* st d,[rs1+%g0] */ +{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, v6 }, +{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, v6 }, +{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", 0, v6 }, +{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, v6 }, /* st d,[rs1+0] */ + +{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, v6 }, +{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", 0, v6 }, /* st d,[rs1+%g0] */ +{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", 0, v6 }, +{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", 0, v6 }, +{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", 0, v6 }, +{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|SIMM13(~0), "F,[1]", 0, v6 }, /* st d,[rs1+0] */ + + /* FIXME-v9: combine st, stw, stuw, stsw, in macros. */ +{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, /* stw === st */ +{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ +{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ +{ "stw", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", F_ALIAS, v9 }, /* st d[rs1+%g0] */ +{ "stw", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ +{ "stw", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ +{ "stw", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ +{ "stw", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ +{ "stw", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ +{ "stw", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ +{ "stw", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|SIMM13(~0), "F,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ + +{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, /* stuw === st */ +{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ +{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ +{ "stuw", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", F_ALIAS, v9 }, /* st d[rs1+%g0] */ +{ "stuw", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ +{ "stuw", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ +{ "stuw", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ +{ "stuw", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ +{ "stuw", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ +{ "stuw", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ +{ "stuw", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|SIMM13(~0), "F,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ + +{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, /* stsw === st */ +{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ +{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ +{ "stsw", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", F_ALIAS, v9 }, /* st d[rs1+%g0] */ +{ "stsw", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ +{ "stsw", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ +{ "stsw", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ +{ "stsw", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ +{ "stsw", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ +{ "stsw", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ +{ "stsw", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|SIMM13(~0), "F,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ + +{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, v6 }, +{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* sta d,[rs1+%g0] */ + +{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, +{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ + +{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, +{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ + +{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, +{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ + +{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, +{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+%g0] */ +{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, v6 }, +{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, v6 }, +{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, v6 }, +{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+0] */ + +{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, +{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* stb d,[rs1+%g0] */ +{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v9 }, +{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v9 }, +{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, +{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* stb d,[rs1+0] */ + +{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, +{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* stb d,[rs1+%g0] */ +{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v9 }, +{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v9 }, +{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, +{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* stb d,[rs1+0] */ + +{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, v6 }, +{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stba d,[rs1+%g0] */ + +{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v9 }, +{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* stba d,[rs1+%g0] */ + +{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v9 }, +{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* stba d,[rs1+%g0] */ + +{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, +{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* std d,[rs1+%g0] */ +{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, v6 }, +{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, v6 }, +{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, v6 }, +{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* std d,[rs1+0] */ +{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, v6 }, +{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, v6 }, /* std d,[rs1+%g0] */ +{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, v6 }, +{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, v6 }, +{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, v6 }, +{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, v6 }, /* std d,[rs1+0] */ +{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "g,[1+2]", 0, v6 }, +{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "g,[1]", 0, v6 }, /* std d,[rs1+%g0] */ +{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "g,[1+i]", 0, v6 }, +{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "g,[i+1]", 0, v6 }, +{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "g,[i]", 0, v6 }, +{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "g,[1]", 0, v6 }, /* std d,[rs1+0] */ +{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, v6 }, +{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, v6 }, /* std d,[rs1+%g0] */ +{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, v6 }, +{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, v6 }, +{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, v6 }, +{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, v6 }, /* std d,[rs1+0] */ +{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, v6 }, +{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, v6 }, /* std d,[rs1+%g0] */ +{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, v6 }, +{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, v6 }, +{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, v6 }, +{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, v6 }, /* std d,[rs1+0] */ + +{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, v6 }, +{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stda d,[rs1+%g0] */ + +{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, +{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+%g0] */ +{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, v6 }, +{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, v6 }, +{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, v6 }, +{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* sth d,[+] */ + +{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, +{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* sth d,[rs1+%g0] */ +{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v9 }, +{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v9 }, +{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, +{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* sth d,[rs1+0] */ + +{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, +{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* sth d,[rs1+%g0] */ +{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v9 }, +{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v9 }, +{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, +{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* sth d,[rs1+0] */ + +{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, v6 }, +{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stha ,[+%] */ + +{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v9 }, +{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* stha d,[rs1+%g0] */ + +{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v9 }, +{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* stha d,[rs1+%g0] */ + +{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, v9 }, +{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+%g0] */ +{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, v9 }, +{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, v9 }, +{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, v9 }, +{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+0] */ +{ "stx", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RD_G0|ASI(~0), "F,[1+2]", F_ALIAS, v9 }, +{ "stx", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ +{ "stx", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RD_G0, "F,[1+i]", F_ALIAS, v9 }, +{ "stx", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RD_G0, "F,[i+1]", F_ALIAS, v9 }, +{ "stx", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RD_G0|RS1_G0, "F,[i]", F_ALIAS, v9 }, +{ "stx", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "F,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ + +{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, v9 }, +{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, v9 }, /* stha d,[rs1+%g0] */ + +{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, v7 }, +{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, v7 }, /* swap [rs1+%g0],d */ +{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, v7 }, +{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, v7 }, +{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, v7 }, +{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, v7 }, /* swap [rs1+0],d */ + +{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, v7 }, +{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, v7 }, /* swapa [rs1+%g0],d */ + +{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v6 }, /* restore %g0,%g0,%g0 */ +{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, v6 }, +{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, v6 }, /* restore %g0,0,%g0 */ + +{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_DELAYED, v6 }, /* rett rs1+rs2 */ +{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_DELAYED, v6 }, /* rett rs1,%g0 */ +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_DELAYED, v6 }, /* rett rs1+X */ +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_DELAYED, v6 }, /* rett X+rs1 */ +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,"i", F_DELAYED, v6 }, /* rett X+rs1 */ +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_DELAYED, v6 }, /* rett X */ +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_DELAYED, v6 }, /* rett rs1+0 */ + +{ "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, v6 }, + +{ "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */ +{ "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */ + +{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_DELAYED, v6 }, +{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_DELAYED, v6 }, /* jmpl rs1+%g0,d */ +{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_DELAYED, v6 }, /* jmpl rs1+0,d */ +{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_DELAYED, v6 }, /* jmpl %g0+i,d */ +{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_DELAYED, v6 }, +{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_DELAYED, v6 }, +{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_DELAYED, v6 }, + + /* The 1<<12 is a long story. It is necessary. For more info, please contact rich@cygnus.com */ +{ "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|ASI(~0), "1,2,d", 0, v6 }, +{ "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12), "1,i,d", 0, v6 }, +{ "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0), "1,2,d", 0, v6 }, +{ "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12), "1,i,d", 0, v6 }, +{ "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0), "1,2,d", 0, v6 }, +{ "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12), "1,i,d", 0, v6 }, + +{ "sllw", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|ASI(~0), "1,2,d", F_ALIAS, v9 }, /* sllw === sll */ +{ "sllw", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12), "1,i,d", F_ALIAS, v9 }, +{ "sraw", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0), "1,2,d", F_ALIAS, v9 }, /* sraw === sra */ +{ "sraw", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12), "1,i,d", F_ALIAS, v9 }, +{ "srlw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0), "1,2,d", F_ALIAS, v9 }, /* srlw === srl */ +{ "srlw", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12), "1,i,d", F_ALIAS, v9 }, + +{ "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(ASI(~0)^(1<<12)), "1,2,d", 0, v9 }, +{ "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1), "1,i,d", 0, v9 }, +{ "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(ASI(~0)^(1<<12)), "1,2,d", 0, v9 }, +{ "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1), "1,i,d", 0, v9 }, +{ "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(ASI(~0)^(1<<12)), "1,2,d", 0, v9 }, +{ "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1), "1,i,d", 0, v9 }, + +{ "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, v6 }, + +{ "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, v6 }, /* or %g0,%g0,d */ +{ "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d", F_ALIAS, v6 }, /* or %g0,0,d */ +{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, +{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */ +{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, +{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, +{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, +{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */ + +{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, +{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */ +{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, +{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, +{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, + +{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, +{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */ +{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, +{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, +{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, + +{ "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, v6 }, +{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, v6 }, + +{ "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, v6 }, +{ "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "i,1,d", 0, v6 }, + +{ "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, v6 }, +{ "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "i,1,d", 0, v6 }, + +{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0, v6 }, /* orcc rs1, %g0, %g0 */ +{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, v6 }, /* orcc %g0, rs2, %g0 */ +{ "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, v6 }, /* orcc rs1, 0, %g0 */ + +{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, v8 }, /* wr r,r,%asrX */ +{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, v6 }, /* wr r,r,%y */ +{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, v8 }, /* wr r,i,%asrX */ +{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, v6 }, /* wr r,i,%y */ +{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, v6 }, /* wr r,r,%psr */ +{ "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, v6 }, /* wr r,i,%psr */ +{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, v6 }, /* wr r,r,%wim */ +{ "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, v6 }, /* wr r,i,%wim */ +{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, v6 }, /* wr r,r,%tbr */ +{ "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, v6 }, /* wr r,i,%tbr */ + +{ "wr", F3(2, 0x30, 0)|RD(0), F3(~2, ~0x30, ~0)|RD(~0)|ASI(~0), "1,2,y", 0, v9 }, +{ "wr", F3(2, 0x30, 1)|RD(0), F3(~2, ~0x30, ~1)|RD(~0), "1,i,y", 0, v9 }, +{ "wr", F3(2, 0x30, 0)|RD(1), F3(~2, ~0x30, ~0)|RD(~1)|ASI(~0), "1,2,E", 0, v9 }, +{ "wr", F3(2, 0x30, 1)|RD(1), F3(~2, ~0x30, ~1)|RD(~1), "1,i,E", 0, v9 }, +{ "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,W", 0, v9 }, +{ "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,W", 0, v9 }, +{ "wr", F3(2, 0x30, 0)|RD(4), F3(~2, ~0x30, ~0)|RD(~4)|ASI(~0), "1,2,p", 0, v9 }, +{ "wr", F3(2, 0x30, 1)|RD(4), F3(~2, ~0x30, ~1)|RD(~4), "1,i,p", 0, v9 }, +{ "wr", F3(2, 0x30, 0)|RD(5), F3(~2, ~0x30, ~0)|RD(~5)|ASI(~0), "1,2,w", 0, v9 }, +{ "wr", F3(2, 0x30, 1)|RD(5), F3(~2, ~0x30, ~1)|RD(~5), "1,i,w", 0, v9 }, + +{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, v8 }, /* rd %asr1,r */ +{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, v6 }, /* rd %y,r */ +{ "rd", F3(2, 0x28, 0)|RS1(1), F3(~2, ~0x28, ~0)|RS1(~1)|SIMM13(~0), "E,d", 0, v9 }, /* rd %modes,r */ +{ "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "P,d", 0, v9 }, /* rd %pc,r */ +{ "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "W,d", 0, v9 }, /* rd %tick,r */ +{ "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "p,d", 0, v9 }, /* rd %psr,r */ +{ "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "w,d", 0, v9 }, /* rd %wim,r */ +{ "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, v6 }, /* rd %tbr,r */ + + /* FIXME-now: the v9 (ie, delta 2.02) definitions of these conflict with the older ones. These are the older ones. */ +{ "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, v6 }, /* rd %psr,r */ +{ "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, v6 }, /* rd %wim,r */ + +{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */ +{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */ +{ "mov", F3(2, 0x30, 0)|RD(0xe), F3(~2, ~0x30, ~0)|RD(~0xe)|ASI(~0), "1,2,Y", F_ALIAS, v9 }, /* wr r,r,%amr */ +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */ +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */ +{ "mov", F3(2, 0x30, 1)|RD(0xe), F3(~2, ~0x30, ~1)|RD(~0xe), "1,i,Y", F_ALIAS, v9 }, /* wr r,i,%amr */ +{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", F_ALIAS, v6 }, /* wr r,r,%psr */ +{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", F_ALIAS, v6 }, /* wr r,i,%psr */ +{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", F_ALIAS, v6 }, /* wr r,r,%wim */ +{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", F_ALIAS, v6 }, /* wr r,i,%wim */ +{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", F_ALIAS, v6 }, /* wr r,r,%tbr */ +{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", F_ALIAS, v6 }, /* wr r,i,%tbr */ + +{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, v8 }, /* rd %asr1,r */ +{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, v6 }, /* rd %y,r */ +{ "mov", F3(2, 0x28, 0)|RS1(0xe), F3(~2, ~0x28, ~0)|RS1(~0xe)|SIMM13(~0), "Y,d", F_ALIAS, v9 }, /* rd %amr,r */ +{ "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, v6 }, /* rd %psr,r */ +{ "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, v6 }, /* rd %wim,r */ +{ "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, v6 }, /* rd %tbr,r */ + +{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "i,y", F_ALIAS, v6 }, +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */ +{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|ASI_RS2(~0), "1,p", F_ALIAS, v6 }, /* wr rs1,%g0,%psr */ +{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1), "i,p", F_ALIAS, v6 }, +{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|SIMM13(~0), "1,p", F_ALIAS, v6 }, /* wr rs1,0,%psr */ +{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|ASI_RS2(~0), "1,w", F_ALIAS, v6 }, /* wr rs1,%g0,%wim */ +{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,w", F_ALIAS, v6 }, +{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|SIMM13(~0), "1,w", F_ALIAS, v6 }, /* wr rs1,0,%wim */ +{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|ASI_RS2(~0), "1,t", F_ALIAS, v6 }, /* wr rs1,%g0,%tbr */ +{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "i,t", F_ALIAS, v6 }, +{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|SIMM13(~0), "1,t", F_ALIAS, v6 }, /* wr rs1,0,%tbr */ + +{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, v6 }, /* or %g0,rs2,d */ +{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d", 0, v6 }, /* or %g0,i,d */ +{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, v6 }, /* or rs1,%g0,d */ +{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, v6 }, /* or rs1,0,d */ + +{ "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, v6 }, +{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, v6 }, + +{ "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* or rd,rs2,rd */ +{ "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, v6 }, /* or rd,i,rd */ + +{ "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, v6 }, +{ "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,1,d", 0, v6 }, + +{ "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, v6 }, +{ "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "i,1,d", 0, v6 }, + +{ "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* andn rd,rs2,rd */ +{ "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, v6 }, /* andn rd,i,rd */ + +{ "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, v6 }, /* subcc rs1,rs2,%g0 */ +{ "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i", 0, v6 }, /* subcc rs1,i,%g0 */ + +{ "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, v6 }, + +{ "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, v6 }, + +{ "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v6 }, + +{ "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v6 }, + +{ "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, v6 }, +{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, v6 }, + +{ "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, v6 }, +{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, v6 }, + +{ "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* sub rd,1,rd */ +{ "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* subcc rd,1,rd */ +{ "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* add rs1,1,rsd */ +{ "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* addcc rd,1,rd */ + +{ "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 }, /* andcc rs1,rs2,%g0 */ +{ "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 }, /* andcc rs1,i,%g0 */ + +{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,rs2,rd */ +{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "r", F_ALIAS, v6 }, /* sub %g0,rd,rd */ + +{ "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, v6 }, +{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, v6 }, +{ "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, v6 }, +{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, v6 }, +{ "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v6 }, +{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v6 }, +{ "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v6 }, +{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v6 }, + +{ "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, v8 }, +{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, v8 }, +{ "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, v8 }, +{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, v8 }, +{ "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, v8 }, +{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, v8 }, +{ "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, v8 }, +{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, v8 }, +{ "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, v8 }, +{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, v8 }, +{ "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, v8 }, +{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, v8 }, +{ "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, v8 }, +{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, v8 }, +{ "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, v8 }, +{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, v8 }, + +{ "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, v9 }, +{ "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, v9 }, +{ "umulxcc", F3(2, 0x19, 0), F3(~2, ~0x19, ~0)|ASI(~0), "1,2,d", 0, v9 }, +{ "umulxcc", F3(2, 0x19, 1), F3(~2, ~0x19, ~1), "1,i,d", 0, v9 }, +{ "sdivxcc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, v9 }, +{ "sdivxcc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, v9 }, +{ "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, v9 }, +{ "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, v9 }, + +{ "call", F1(0x1), F1(~0x1), "L", F_DELAYED, v6 }, +{ "call", F1(0x1), F1(~0x1), "L,#", F_DELAYED, v6 }, +{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_DELAYED, v6 }, /* jmpl rs1+%g0, %o7 */ +{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_DELAYED, v6 }, + +/* Conditional instructions. + + Because this part of the table was such a mess earlier, I have + macrofied it so that all the branches and traps are generated from + a single-line description of each condition value. John Gilmore. */ + +/* Define branches -- one annulled, one without, etc. */ +#define br(opcode, mask, lose, flags) \ + { opcode, (mask)|ANNUL, (lose), ",a l", (flags), v6 }, \ + { opcode, (mask) , (lose)|ANNUL, "l", (flags), v6 } + +#define brx(opcode, mask, lose, flags) /* v9 */ \ + { opcode, (mask), (lose)|ANNUL|BPRED, "Z,G", (flags), v9 }, \ + { opcode, (mask), (lose)|ANNUL|BPRED, ",N Z,G", (flags), v9 }, \ + { opcode, (mask)|ANNUL, (lose)|BPRED, ",a Z,G", (flags), v9 }, \ + { opcode, (mask)|ANNUL, (lose)|BPRED, ",a,N Z,G", (flags), v9 }, \ + { opcode, (mask)|BPRED, (lose)|ANNUL, ",T Z,G", (flags), v9 }, \ + { opcode, (mask)|ANNUL|BPRED, (lose), ",a,T Z,G", (flags), v9 }, \ + { opcode, (mask), (lose)|ANNUL|BPRED, "z,G", (flags), v9 }, \ + { opcode, (mask), (lose)|ANNUL|BPRED, ",N z,G", (flags), v9 }, \ + { opcode, (mask)|ANNUL, (lose)|BPRED, ",a z,G", (flags), v9 }, \ + { opcode, (mask)|ANNUL, (lose)|BPRED, ",a,N z,G", (flags), v9 }, \ + { opcode, (mask)|BPRED, (lose)|ANNUL, ",T z,G", (flags), v9 }, \ + { opcode, (mask)|ANNUL|BPRED, (lose), ",a,T z,G", (flags), v9 } + +/* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */ +#define tr(opcode, mask, lose, flags) \ + { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), v6 }, /* %g0 + imm */ \ + { opcode, (mask)|IMMED, (lose), "1+i", (flags), v6 }, /* rs1 + imm */ \ + { opcode, (mask), IMMED|(lose), "1+2", (flags), v6 }, /* rs1 + rs2 */ \ + { opcode, (mask)|(1<<12)|IMMED, (lose)|RS1_G0, "Z,i", (flags), v9 }, /* %g0 + imm */ \ + { opcode, (mask)|(1<<12)|IMMED, (lose), "Z,1+i", (flags), v9 }, /* rs1 + imm */ \ + { opcode, (mask)|(1<<12), IMMED|(lose), "Z,1+2", (flags), v9 }, /* rs1 + rs2 */ \ + { opcode, (mask)|(1<<12), IMMED|(lose)|RS2_G0, "Z,1", (flags), v9 }, /* rs1 + %g0 */ \ + { opcode, (mask)|IMMED, (1<<12)|(lose)|RS1_G0, "z,i", (flags)|F_ALIAS, v9 }, /* %g0 + imm */ \ + { opcode, (mask)|IMMED, (1<<12)|(lose), "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1 + imm */ \ + { opcode, (mask), IMMED|(1<<12)|(lose), "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1 + rs2 */ \ + { opcode, (mask), IMMED|(1<<12)|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \ + { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), v6 } /* rs1 + %g0 */ + +/* Define both branches and traps based on condition mask */ +#define cond(bop, top, mask, flags) \ + br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \ + brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \ + tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), (flags)) + +/* Define all the conditions, all the branches, all the traps. */ + +cond ("b", "t", CONDA, 0), +cond ("ba", "ta", CONDA, F_ALIAS), /* for nothing */ +cond ("bcc", "tcc", CONDCC, 0), +cond ("bcs", "tcs", CONDCS, 0), +cond ("be", "te", CONDE, 0), +cond ("bg", "tg", CONDG, 0), +cond ("bgt", "tgt", CONDG, F_ALIAS), +cond ("bge", "tge", CONDGE, 0), +cond ("bgeu", "tgeu", CONDGEU, F_ALIAS), /* for cc */ +cond ("bgu", "tgu", CONDGU, 0), +cond ("bl", "tl", CONDL, 0), +cond ("blt", "tlt", CONDL, F_ALIAS), +cond ("ble", "tle", CONDLE, 0), +cond ("bleu", "tleu", CONDLEU, 0), +cond ("blu", "tlu", CONDLU, F_ALIAS), /* for cs */ +cond ("bn", "tn", CONDN, 0), +cond ("bne", "tne", CONDNE, 0), +cond ("bneg", "tneg", CONDNEG, 0), +cond ("bnz", "tnz", CONDNZ, F_ALIAS), /* for ne */ +cond ("bpos", "tpos", CONDPOS, 0), +cond ("bvc", "tvc", CONDVC, 0), +cond ("bvs", "tvs", CONDVS, 0), +cond ("bz", "tz", CONDZ, F_ALIAS), /* for e */ + +#undef cond +#undef br +#undef tr + +#define brr(opcode, mask, lose, flags) /* v9 */ \ + { opcode, (mask), (lose)|ANNUL|BPRED, "1,k", F_DELAYED|(flags), v9 }, \ + { opcode, (mask), (lose)|ANNUL|BPRED, ",N 1,k", F_DELAYED|(flags), v9 }, \ + { opcode, (mask)|ANNUL, (lose)|BPRED, ",a 1,k", F_DELAYED|(flags), v9 }, \ + { opcode, (mask)|ANNUL, (lose)|BPRED, ",a,N 1,k", F_DELAYED|(flags), v9 }, \ + { opcode, (mask)|BPRED, (lose)|ANNUL, ",T 1,k", F_DELAYED|(flags), v9 }, \ + { opcode, (mask)|ANNUL|BPRED, (lose), ",a,T 1,k", F_DELAYED|(flags), v9 } + +#define condr(bop, mask, flags) /* v9 */ \ + brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */ \ + +/* v9 */ condr("bre", 0x1, 0), +/* v9 */ condr("brne", 0x0, 0), +/* v9 */ condr("brneg", 0x3, 0), +/* v9 */ condr("brnz", 0x0, F_ALIAS), +/* v9 */ condr("brpos", 0x2, 0), +/* v9 */ condr("brz", 0x1, F_ALIAS), + +#undef condr /* v9 */ +#undef brr /* v9 */ + +#define mrr(opcode, mask, lose, flags) /* v9 */ \ + { opcode, (mask), (lose)|ASI(~0), "1,2,d", F_DELAYED|(flags), v9 }, \ + { opcode, (mask), (lose), "1,i,d", F_DELAYED|(flags), v9 } + +#define movr(bop, mask, flags) /* v9 */ \ + mrr(bop, F3(2, 0x2f, 0)|COND(mask), F3(~2, ~0x2f, ~0)|COND(~(mask))|ASI(~0), (flags)), /* v9 */ \ + mrr(bop, F3(2, 0x2f, 1)|COND(mask), F3(~2, ~0x2f, ~1)|COND(~(mask)), (flags)) /* v9 */ \ + +/* v9 */ movr("movre", 0x1, 0), +/* v9 */ movr("movrne", 0x0, 0), +/* v9 */ movr("movrneg", 0x3, 0), +/* v9 */ movr("movrnz", 0x0, F_ALIAS), +/* v9 */ movr("movrpos", 0x2, 0), +/* v9 */ movr("movrz", 0x1, F_ALIAS), + +#undef movr /* v9 */ +#undef mrr /* v9 */ + +{ "mova", F3(2, 0x58, 0)|FCC(0)|MCOND(FCONDA), MCOND(~FCONDA)|FCC(~0)|F3(~2, ~0x58, ~0), "6,2,d", 0, v9 }, +{ "mova", F3(2, 0x58, 1)|FCC(0)|MCOND(FCONDA), MCOND(~FCONDA)|FCC(~0)|F3(~2, ~0x58,~1), "6,I,d", 0, v9 }, +{ "mova", F3(2, 0x58, 0)|FCC(1)|MCOND(FCONDA), MCOND(~FCONDA)|FCC(~1)|F3(~2, ~0x58, ~0), "7,2,d", 0, v9 }, +{ "mova", F3(2, 0x58, 1)|FCC(1)|MCOND(FCONDA), MCOND(~FCONDA)|FCC(~1)|F3(~2, ~0x58, ~1), "7,I,d", 0, v9 }, +{ "mova", F3(2, 0x58, 0)|FCC(2)|MCOND(FCONDA), MCOND(~FCONDA)|FCC(~2)|F3(~2, ~0x58, ~0), "8,2,d", 0, v9 }, +{ "mova", F3(2, 0x58, 1)|FCC(2)|MCOND(FCONDA), MCOND(~FCONDA)|FCC(~2)|F3(~2, ~0x58, ~1), "8,I,d", 0, v9 }, +{ "mova", F3(2, 0x58, 0)|FCC(3)|MCOND(FCONDA), MCOND(~FCONDA)|FCC(~3)|F3(~2, ~0x58, ~0), "9,2,d", 0, v9 }, +{ "mova", F3(2, 0x58, 1)|FCC(3)|MCOND(FCONDA), MCOND(~FCONDA)|FCC(~3)|F3(~2, ~0x58, ~1), "9,I,d", 0, v9 }, +{ "mova", F3(2, 0x59, 0)|MCOND(CONDA)|ICC, F3(~2, ~0x59, ~0)|MCOND(~CONDA)|XCC|(1<<12), "z,2,d", 0, v9 }, +{ "mova", F3(2, 0x59, 1)|MCOND(CONDA)|ICC, F3(~2, ~0x59, ~1)|MCOND(~CONDA)|XCC|(1<<12), "z,I,d", 0, v9 }, +{ "mova", F3(2, 0x59, 0)|MCOND(CONDA)|XCC, F3(~2, ~0x59, ~0)|MCOND(~CONDA)|(1<<12), "Z,2,d", 0, v9 }, +{ "mova", F3(2, 0x59, 1)|MCOND(CONDA)|XCC, F3(~2, ~0x59, ~1)|MCOND(~CONDA)|(1<<12), "Z,I,d", 0, v9 }, +{ "movcc", F3(2, 0x59, 0)|MCOND(CONDCC)|ICC, F3(~2, ~0x59, ~0)|MCOND(~CONDCC)|XCC|(1<<12), "z,2,d", 0, v9 }, +{ "movcc", F3(2, 0x59, 1)|MCOND(CONDCC)|ICC, F3(~2, ~0x59, ~1)|MCOND(~CONDCC)|XCC|(1<<12), "z,I,d", 0, v9 }, +{ "movcc", F3(2, 0x59, 0)|MCOND(CONDCC)|XCC, F3(~2, ~0x59, ~0)|MCOND(~CONDCC)|(1<<12), "Z,2,d", 0, v9 }, +{ "movcc", F3(2, 0x59, 1)|MCOND(CONDCC)|XCC, F3(~2, ~0x59, ~1)|MCOND(~CONDCC)|(1<<12), "Z,I,d", 0, v9 }, +{ "movgeu", F3(2, 0x59, 0)|MCOND(CONDGEU)|ICC, F3(~2, ~0x59, ~0)|MCOND(~CONDGEU)|XCC|(1<<12), "z,2,d", 0, v9 }, +{ "movgeu", F3(2, 0x59, 1)|MCOND(CONDGEU)|ICC, F3(~2, ~0x59, ~1)|MCOND(~CONDGEU)|XCC|(1<<12), "z,I,d", 0, v9 }, +{ "movgeu", F3(2, 0x59, 0)|MCOND(CONDGEU)|XCC, F3(~2, ~0x59, ~0)|MCOND(~CONDGEU)|(1<<12), "Z,2,d", 0, v9 }, +{ "movgeu", F3(2, 0x59, 1)|MCOND(CONDGEU)|XCC, F3(~2, ~0x59, ~1)|MCOND(~CONDGEU)|(1<<12), "Z,I,d", 0, v9 }, +{ "movcs", F3(2, 0x59, 0)|MCOND(CONDCS)|ICC, F3(~2, ~0x59, ~0)|MCOND(~CONDCS)|XCC|(1<<12), "z,2,d", 0, v9 }, +{ "movcs", F3(2, 0x59, 1)|MCOND(CONDCS)|ICC, F3(~2, ~0x59, ~1)|MCOND(~CONDCS)|XCC|(1<<12), "z,I,d", 0, v9 }, +{ "movcs", F3(2, 0x59, 0)|MCOND(CONDCS)|XCC, F3(~2, ~0x59, ~0)|MCOND(~CONDCS)|(1<<12), "Z,2,d", 0, v9 }, +{ "movcs", F3(2, 0x59, 1)|MCOND(CONDCS)|XCC, F3(~2, ~0x59, ~1)|MCOND(~CONDCS)|(1<<12), "Z,I,d", 0, v9 }, +{ "movlu", F3(2, 0x59, 0)|MCOND(CONDLU)|ICC, F3(~2, ~0x59, ~0)|MCOND(~CONDLU)|XCC|(1<<12), "z,2,d", 0, v9 }, +{ "movlu", F3(2, 0x59, 1)|MCOND(CONDLU)|ICC, F3(~2, ~0x59, ~1)|MCOND(~CONDLU)|XCC|(1<<12), "z,I,d", 0, v9 }, +{ "movlu", F3(2, 0x59, 0)|MCOND(CONDLU)|XCC, F3(~2, ~0x59, ~0)|MCOND(~CONDLU)|(1<<12), "Z,2,d", 0, v9 }, +{ "movlu", F3(2, 0x59, 1)|MCOND(CONDLU)|XCC, F3(~2, ~0x59, ~1)|MCOND(~CONDLU)|(1<<12), "Z,I,d", 0, v9 }, +{ "move", F3(2, 0x58, 0)|FCC(0)|MCOND(FCONDE), MCOND(~FCONDE)|FCC(~0)|F3(~2, ~0x58, ~0), "6,2,d", 0, v9 }, +{ "move", F3(2, 0x58, 1)|FCC(0)|MCOND(FCONDE), MCOND(~FCONDE)|FCC(~0)|F3(~2, ~0x58, ~1), "6,I,d", 0, v9 }, +{ "move", F3(2, 0x58, 0)|FCC(1)|MCOND(FCONDE), MCOND(~FCONDE)|FCC(~1)|F3(~2, ~0x58, ~0), "7,2,d", 0, v9 }, +{ "move", F3(2, 0x58, 1)|FCC(1)|MCOND(FCONDE), MCOND(~FCONDE)|FCC(~1)|F3(~2, ~0x58, ~1), "7,I,d", 0, v9 }, +{ "move", F3(2, 0x58, 0)|FCC(2)|MCOND(FCONDE), MCOND(~FCONDE)|FCC(~2)|F3(~2, ~0x58, ~0), "8,2,d", 0, v9 }, +{ "move", F3(2, 0x58, 1)|FCC(2)|MCOND(FCONDE), MCOND(~FCONDE)|FCC(~2)|F3(~2, ~0x58, ~1), "8,I,d", 0, v9 }, +{ "move", F3(2, 0x58, 0)|FCC(3)|MCOND(FCONDE), MCOND(~FCONDE)|FCC(~3)|F3(~2, ~0x58, ~0), "9,2,d", 0, v9 }, +{ "move", F3(2, 0x58, 1)|FCC(3)|MCOND(FCONDE), MCOND(~FCONDE)|FCC(~3)|F3(~2, ~0x58, ~1), "9,I,d", 0, v9 }, +{ "move", F3(2, 0x59, 0)|MCOND(CONDE)|ICC, F3(~2, ~0x59, ~0)|MCOND(~CONDE)|XCC|(1<<12), "z,2,d", 0, v9 }, +{ "move", F3(2, 0x59, 1)|MCOND(CONDE)|ICC, F3(~2, ~0x59, ~1)|MCOND(~CONDE)|XCC|(1<<12), "z,I,d", 0, v9 }, +{ "move", F3(2, 0x59, 0)|MCOND(CONDE)|XCC, F3(~2, ~0x59, ~0)|MCOND(~CONDE)|(1<<12), "Z,2,d", 0, v9 }, +{ "move", F3(2, 0x59, 1)|MCOND(CONDE)|XCC, F3(~2, ~0x59, ~1)|MCOND(~CONDE)|(1<<12), "Z,I,d", 0, v9 }, +{ "movg", F3(2, 0x58, 0)|FCC(0)|MCOND(FCONDG), MCOND(~FCONDG)|FCC(~0)|F3(~2, ~0x58, ~0), "6,2,d", 0, v9 }, +{ "movg", F3(2, 0x58, 1)|FCC(0)|MCOND(FCONDG), MCOND(~FCONDG)|FCC(~0)|F3(~2, ~0x58, ~1), "6,I,d", 0, v9 }, +{ "movg", F3(2, 0x58, 0)|FCC(1)|MCOND(FCONDG), MCOND(~FCONDG)|FCC(~1)|F3(~2, ~0x58, ~0), "7,2,d", 0, v9 }, +{ "movg", F3(2, 0x58, 1)|FCC(1)|MCOND(FCONDG), MCOND(~FCONDG)|FCC(~1)|F3(~2, ~0x58, ~1), "7,I,d", 0, v9 }, +{ "movg", F3(2, 0x58, 0)|FCC(2)|MCOND(FCONDG), MCOND(~FCONDG)|FCC(~2)|F3(~2, ~0x58, ~0), "8,2,d", 0, v9 }, +{ "movg", F3(2, 0x58, 1)|FCC(2)|MCOND(FCONDG), MCOND(~FCONDG)|FCC(~2)|F3(~2, ~0x58, ~1), "8,I,d", 0, v9 }, +{ "movg", F3(2, 0x58, 0)|FCC(3)|MCOND(FCONDG), MCOND(~FCONDG)|FCC(~3)|F3(~2, ~0x58, ~0), "9,2,d", 0, v9 }, +{ "movg", F3(2, 0x58, 1)|FCC(3)|MCOND(FCONDG), MCOND(~FCONDG)|FCC(~3)|F3(~2, ~0x58, ~1), "9,I,d", 0, v9 }, +{ "movg", F3(2, 0x59, 0)|MCOND(CONDG)|ICC, F3(~2, ~0x59, ~0)|MCOND(~CONDG)|XCC|(1<<12), "z,2,d", 0, v9 }, +{ "movg", F3(2, 0x59, 1)|MCOND(CONDG)|ICC, F3(~2, ~0x59, ~1)|MCOND(~CONDG)|XCC|(1<<12), "z,I,d", 0, v9 }, +{ "movg", F3(2, 0x59, 0)|MCOND(CONDG)|XCC, F3(~2, ~0x59, ~0)|MCOND(~CONDG)|(1<<12), "Z,2,d", 0, v9 }, +{ "movg", F3(2, 0x59, 1)|MCOND(CONDG)|XCC, F3(~2, ~0x59, ~1)|MCOND(~CONDG)|(1<<12), "Z,I,d", 0, v9 }, +{ "movge", F3(2, 0x58, 0)|FCC(0)|MCOND(FCONDGE), MCOND(~FCONDGE)|FCC(~0)|F3(~2, ~0x58, ~0), "6,2,d", 0, v9 }, +{ "movge", F3(2, 0x58, 1)|FCC(0)|MCOND(FCONDGE), MCOND(~FCONDGE)|FCC(~0)|F3(~2, ~0x58, ~1), "6,I,d", 0, v9 }, +{ "movge", F3(2, 0x58, 0)|FCC(1)|MCOND(FCONDGE), MCOND(~FCONDGE)|FCC(~1)|F3(~2, ~0x58, ~0), "7,2,d", 0, v9 }, +{ "movge", F3(2, 0x58, 1)|FCC(1)|MCOND(FCONDGE), MCOND(~FCONDGE)|FCC(~1)|F3(~2, ~0x58, ~1), "7,I,d", 0, v9 }, +{ "movge", F3(2, 0x58, 0)|FCC(2)|MCOND(FCONDGE), MCOND(~FCONDGE)|FCC(~2)|F3(~2, ~0x58, ~0), "8,2,d", 0, v9 }, +{ "movge", F3(2, 0x58, 1)|FCC(2)|MCOND(FCONDGE), MCOND(~FCONDGE)|FCC(~2)|F3(~2, ~0x58, ~1), "8,I,d", 0, v9 }, +{ "movge", F3(2, 0x58, 0)|FCC(3)|MCOND(FCONDGE), MCOND(~FCONDGE)|FCC(~3)|F3(~2, ~0x58, ~0), "9,2,d", 0, v9 }, +{ "movge", F3(2, 0x58, 1)|FCC(3)|MCOND(FCONDGE), MCOND(~FCONDGE)|FCC(~3)|F3(~2, ~0x58, ~1), "9,I,d", 0, v9 }, +{ "movge", F3(2, 0x59, 0)|MCOND(CONDGE)|ICC, F3(~2, ~0x59, ~0)|MCOND(~CONDGE)|XCC|(1<<12), "z,2,d", 0, v9 }, +{ "movge", F3(2, 0x59, 1)|MCOND(CONDGE)|ICC, F3(~2, ~0x59, ~1)|MCOND(~CONDGE)|XCC|(1<<12), "z,I,d", 0, v9 }, +{ "movge", F3(2, 0x59, 0)|MCOND(CONDGE)|XCC, F3(~2, ~0x59, ~0)|MCOND(~CONDGE)|(1<<12), "Z,2,d", 0, v9 }, +{ "movge", F3(2, 0x59, 1)|MCOND(CONDGE)|XCC, F3(~2, ~0x59, ~1)|MCOND(~CONDGE)|(1<<12), "Z,I,d", 0, v9 }, +{ "movgu", F3(2, 0x59, 0)|MCOND(CONDGU)|ICC, F3(~2, ~0x59, ~0)|MCOND(~CONDGU)|XCC|(1<<12), "z,2,d", 0, v9 }, +{ "movgu", F3(2, 0x59, 1)|MCOND(CONDGU)|ICC, F3(~2, ~0x59, ~1)|MCOND(~CONDGU)|XCC|(1<<12), "z,I,d", 0, v9 }, +{ "movgu", F3(2, 0x59, 0)|MCOND(CONDGU)|XCC, F3(~2, ~0x59, ~0)|MCOND(~CONDGU)|(1<<12), "Z,2,d", 0, v9 }, +{ "movgu", F3(2, 0x59, 1)|MCOND(CONDGU)|XCC, F3(~2, ~0x59, ~1)|MCOND(~CONDGU)|(1<<12), "Z,I,d", 0, v9 }, +{ "movl", F3(2, 0x58, 0)|FCC(0)|MCOND(FCONDL), MCOND(~FCONDL)|FCC(~0)|F3(~2, ~0x58, ~0), "6,2,d", 0, v9 }, +{ "movl", F3(2, 0x58, 1)|FCC(0)|MCOND(FCONDL), MCOND(~FCONDL)|FCC(~0)|F3(~2, ~0x58, ~1), "6,I,d", 0, v9 }, +{ "movl", F3(2, 0x58, 0)|FCC(1)|MCOND(FCONDL), MCOND(~FCONDL)|FCC(~1)|F3(~2, ~0x58, ~0), "7,2,d", 0, v9 }, +{ "movl", F3(2, 0x58, 1)|FCC(1)|MCOND(FCONDL), MCOND(~FCONDL)|FCC(~1)|F3(~2, ~0x58, ~1), "7,I,d", 0, v9 }, +{ "movl", F3(2, 0x58, 0)|FCC(2)|MCOND(FCONDL), MCOND(~FCONDL)|FCC(~2)|F3(~2, ~0x58, ~0), "8,2,d", 0, v9 }, +{ "movl", F3(2, 0x58, 1)|FCC(2)|MCOND(FCONDL), MCOND(~FCONDL)|FCC(~2)|F3(~2, ~0x58, ~1), "8,I,d", 0, v9 }, +{ "movl", F3(2, 0x58, 0)|FCC(3)|MCOND(FCONDL), MCOND(~FCONDL)|FCC(~3)|F3(~2, ~0x58, ~0), "9,2,d", 0, v9 }, +{ "movl", F3(2, 0x58, 1)|FCC(3)|MCOND(FCONDL), MCOND(~FCONDL)|FCC(~3)|F3(~2, ~0x58, ~1), "9,I,d", 0, v9 }, +{ "movl", F3(2, 0x59, 0)|MCOND(CONDL)|ICC, F3(~2, ~0x59, ~0)|MCOND(~CONDL)|XCC|(1<<12), "z,2,d", 0, v9 }, +{ "movl", F3(2, 0x59, 1)|MCOND(CONDL)|ICC, F3(~2, ~0x59, ~1)|MCOND(~CONDL)|XCC|(1<<12), "z,I,d", 0, v9 }, +{ "movl", F3(2, 0x59, 0)|MCOND(CONDL)|XCC, F3(~2, ~0x59, ~0)|MCOND(~CONDL)|(1<<12), "Z,2,d", 0, v9 }, +{ "movl", F3(2, 0x59, 1)|MCOND(CONDL)|XCC, F3(~2, ~0x59, ~1)|MCOND(~CONDL)|(1<<12), "Z,I,d", 0, v9 }, +{ "movle", F3(2, 0x58, 0)|FCC(0)|MCOND(FCONDLE), MCOND(~FCONDLE)|FCC(~0)|F3(~2, ~0x58, ~0), "6,2,d", 0, v9 }, +{ "movle", F3(2, 0x58, 1)|FCC(0)|MCOND(FCONDLE), MCOND(~FCONDLE)|FCC(~0)|F3(~2, ~0x58, ~1), "6,I,d", 0, v9 }, +{ "movle", F3(2, 0x58, 0)|FCC(1)|MCOND(FCONDLE), MCOND(~FCONDLE)|FCC(~1)|F3(~2, ~0x58, ~0), "7,2,d", 0, v9 }, +{ "movle", F3(2, 0x58, 1)|FCC(1)|MCOND(FCONDLE), MCOND(~FCONDLE)|FCC(~1)|F3(~2, ~0x58, ~1), "7,I,d", 0, v9 }, +{ "movle", F3(2, 0x58, 0)|FCC(2)|MCOND(FCONDLE), MCOND(~FCONDLE)|FCC(~2)|F3(~2, ~0x58, ~0), "8,2,d", 0, v9 }, +{ "movle", F3(2, 0x58, 1)|FCC(2)|MCOND(FCONDLE), MCOND(~FCONDLE)|FCC(~2)|F3(~2, ~0x58, ~1), "8,I,d", 0, v9 }, +{ "movle", F3(2, 0x58, 0)|FCC(3)|MCOND(FCONDLE), MCOND(~FCONDLE)|FCC(~3)|F3(~2, ~0x58, ~0), "9,2,d", 0, v9 }, +{ "movle", F3(2, 0x58, 1)|FCC(3)|MCOND(FCONDLE), MCOND(~FCONDLE)|FCC(~3)|F3(~2, ~0x58, ~1), "9,I,d", 0, v9 }, +{ "movle", F3(2, 0x59, 0)|MCOND(CONDLE)|ICC, F3(~2, ~0x59, ~0)|MCOND(~CONDLE)|XCC|(1<<12), "z,2,d", 0, v9 }, +{ "movle", F3(2, 0x59, 1)|MCOND(CONDLE)|ICC, F3(~2, ~0x59, ~1)|MCOND(~CONDLE)|XCC|(1<<12), "z,I,d", 0, v9 }, +{ "movle", F3(2, 0x59, 0)|MCOND(CONDLE)|XCC, F3(~2, ~0x59, ~0)|MCOND(~CONDLE)|(1<<12), "Z,2,d", 0, v9 }, +{ "movle", F3(2, 0x59, 1)|MCOND(CONDLE)|XCC, F3(~2, ~0x59, ~1)|MCOND(~CONDLE)|(1<<12), "Z,I,d", 0, v9 }, +{ "movleu", F3(2, 0x59, 0)|MCOND(CONDLEU)|ICC, F3(~2, ~0x59, ~0)|MCOND(~CONDLEU)|XCC|(1<<12), "z,2,d", 0, v9 }, +{ "movleu", F3(2, 0x59, 1)|MCOND(CONDLEU)|ICC, F3(~2, ~0x59, ~1)|MCOND(~CONDLEU)|XCC|(1<<12), "z,I,d", 0, v9 }, +{ "movleu", F3(2, 0x59, 0)|MCOND(CONDLEU)|XCC, F3(~2, ~0x59, ~0)|MCOND(~CONDLEU)|(1<<12), "Z,2,d", 0, v9 }, +{ "movleu", F3(2, 0x59, 1)|MCOND(CONDLEU)|XCC, F3(~2, ~0x59, ~1)|MCOND(~CONDLEU)|(1<<12), "Z,I,d", 0, v9 }, +{ "movlg", F3(2, 0x58, 0)|FCC(0)|MCOND(FCONDLG), MCOND(~FCONDLG)|FCC(~0)|F3(~2, ~0x58, ~0), "6,2,d", 0, v9 }, +{ "movlg", F3(2, 0x58, 1)|FCC(0)|MCOND(FCONDLG), MCOND(~FCONDLG)|FCC(~0)|F3(~2, ~0x58, ~1), "6,I,d", 0, v9 }, +{ "movlg", F3(2, 0x58, 0)|FCC(1)|MCOND(FCONDLG), MCOND(~FCONDLG)|FCC(~1)|F3(~2, ~0x58, ~0), "7,2,d", 0, v9 }, +{ "movlg", F3(2, 0x58, 1)|FCC(1)|MCOND(FCONDLG), MCOND(~FCONDLG)|FCC(~1)|F3(~2, ~0x58, ~1), "7,I,d", 0, v9 }, +{ "movlg", F3(2, 0x58, 0)|FCC(2)|MCOND(FCONDLG), MCOND(~FCONDLG)|FCC(~2)|F3(~2, ~0x58, ~0), "8,2,d", 0, v9 }, +{ "movlg", F3(2, 0x58, 1)|FCC(2)|MCOND(FCONDLG), MCOND(~FCONDLG)|FCC(~2)|F3(~2, ~0x58, ~1), "8,I,d", 0, v9 }, +{ "movlg", F3(2, 0x58, 0)|FCC(3)|MCOND(FCONDLG), MCOND(~FCONDLG)|FCC(~3)|F3(~2, ~0x58, ~0), "9,2,d", 0, v9 }, +{ "movlg", F3(2, 0x58, 1)|FCC(3)|MCOND(FCONDLG), MCOND(~FCONDLG)|FCC(~3)|F3(~2, ~0x58, ~1), "9,I,d", 0, v9 }, +{ "movn", F3(2, 0x58, 0)|FCC(0)|MCOND(FCONDN), MCOND(~FCONDN)|FCC(~0)|F3(~2, ~0x58, ~0), "6,2,d", 0, v9 }, +{ "movn", F3(2, 0x58, 1)|FCC(0)|MCOND(FCONDN), MCOND(~FCONDN)|FCC(~0)|F3(~2, ~0x58, ~1), "6,I,d", 0, v9 }, +{ "movn", F3(2, 0x58, 0)|FCC(1)|MCOND(FCONDN), MCOND(~FCONDN)|FCC(~1)|F3(~2, ~0x58, ~0), "7,2,d", 0, v9 }, +{ "movn", F3(2, 0x58, 1)|FCC(1)|MCOND(FCONDN), MCOND(~FCONDN)|FCC(~1)|F3(~2, ~0x58, ~1), "7,I,d", 0, v9 }, +{ "movn", F3(2, 0x58, 0)|FCC(2)|MCOND(FCONDN), MCOND(~FCONDN)|FCC(~2)|F3(~2, ~0x58, ~0), "8,2,d", 0, v9 }, +{ "movn", F3(2, 0x58, 1)|FCC(2)|MCOND(FCONDN), MCOND(~FCONDN)|FCC(~2)|F3(~2, ~0x58, ~1), "8,I,d", 0, v9 }, +{ "movn", F3(2, 0x58, 0)|FCC(3)|MCOND(FCONDN), MCOND(~FCONDN)|FCC(~3)|F3(~2, ~0x58, ~0), "9,2,d", 0, v9 }, +{ "movn", F3(2, 0x58, 1)|FCC(3)|MCOND(FCONDN), MCOND(~FCONDN)|FCC(~3)|F3(~2, ~0x58, ~1), "9,I,d", 0, v9 }, +{ "movn", F3(2, 0x59, 0)|MCOND(CONDN)|ICC, F3(~2, ~0x59, ~0)|MCOND(~CONDN)|XCC|(1<<12), "z,2,d", 0, v9 }, +{ "movn", F3(2, 0x59, 1)|MCOND(CONDN)|ICC, F3(~2, ~0x59, ~1)|MCOND(~CONDN)|XCC|(1<<12), "z,I,d", 0, v9 }, +{ "movn", F3(2, 0x59, 0)|MCOND(CONDN)|XCC, F3(~2, ~0x59, ~0)|MCOND(~CONDN)|(1<<12), "Z,2,d", 0, v9 }, +{ "movn", F3(2, 0x59, 1)|MCOND(CONDN)|XCC, F3(~2, ~0x59, ~1)|MCOND(~CONDN)|(1<<12), "Z,I,d", 0, v9 }, +{ "movne", F3(2, 0x58, 0)|FCC(0)|MCOND(FCONDNE), MCOND(~FCONDNE)|FCC(~0)|F3(~2, ~0x58, ~0), "6,2,d", 0, v9 }, +{ "movne", F3(2, 0x58, 1)|FCC(0)|MCOND(FCONDNE), MCOND(~FCONDNE)|FCC(~0)|F3(~2, ~0x58, ~1), "6,I,d", 0, v9 }, +{ "movne", F3(2, 0x58, 0)|FCC(1)|MCOND(FCONDNE), MCOND(~FCONDNE)|FCC(~1)|F3(~2, ~0x58, ~0), "7,2,d", 0, v9 }, +{ "movne", F3(2, 0x58, 1)|FCC(1)|MCOND(FCONDNE), MCOND(~FCONDNE)|FCC(~1)|F3(~2, ~0x58, ~1), "7,I,d", 0, v9 }, +{ "movne", F3(2, 0x58, 0)|FCC(2)|MCOND(FCONDNE), MCOND(~FCONDNE)|FCC(~2)|F3(~2, ~0x58, ~0), "8,2,d", 0, v9 }, +{ "movne", F3(2, 0x58, 1)|FCC(2)|MCOND(FCONDNE), MCOND(~FCONDNE)|FCC(~2)|F3(~2, ~0x58, ~1), "8,I,d", 0, v9 }, +{ "movne", F3(2, 0x58, 0)|FCC(3)|MCOND(FCONDNE), MCOND(~FCONDNE)|FCC(~3)|F3(~2, ~0x58, ~0), "9,2,d", 0, v9 }, +{ "movne", F3(2, 0x58, 1)|FCC(3)|MCOND(FCONDNE), MCOND(~FCONDNE)|FCC(~3)|F3(~2, ~0x58, ~1), "9,I,d", 0, v9 }, +{ "movne", F3(2, 0x59, 0)|MCOND(CONDNE)|ICC, F3(~2, ~0x59, ~0)|MCOND(~CONDNE)|XCC|(1<<12), "z,2,d", 0, v9 }, +{ "movne", F3(2, 0x59, 1)|MCOND(CONDNE)|ICC, F3(~2, ~0x59, ~1)|MCOND(~CONDNE)|XCC|(1<<12), "z,I,d", 0, v9 }, +{ "movne", F3(2, 0x59, 0)|MCOND(CONDNE)|XCC, F3(~2, ~0x59, ~0)|MCOND(~CONDNE)|(1<<12), "Z,2,d", 0, v9 }, +{ "movne", F3(2, 0x59, 1)|MCOND(CONDNE)|XCC, F3(~2, ~0x59, ~1)|MCOND(~CONDNE)|(1<<12), "Z,I,d", 0, v9 }, +{ "movneg", F3(2, 0x59, 0)|MCOND(CONDNEG)|ICC, F3(~2, ~0x59, ~0)|MCOND(~CONDNEG)|XCC|(1<<12), "z,2,d", 0, v9 }, +{ "movneg", F3(2, 0x59, 1)|MCOND(CONDNEG)|ICC, F3(~2, ~0x59, ~1)|MCOND(~CONDNEG)|XCC|(1<<12), "z,I,d", 0, v9 }, +{ "movneg", F3(2, 0x59, 0)|MCOND(CONDNEG)|XCC, F3(~2, ~0x59, ~0)|MCOND(~CONDNEG)|(1<<12), "Z,2,d", 0, v9 }, +{ "movneg", F3(2, 0x59, 1)|MCOND(CONDNEG)|XCC, F3(~2, ~0x59, ~1)|MCOND(~CONDNEG)|(1<<12), "Z,I,d", 0, v9 }, +{ "movnz", F3(2, 0x58, 0)|FCC(0)|MCOND(FCONDNZ), MCOND(~FCONDNZ)|FCC(~0)|F3(~2, ~0x58, ~0), "6,2,d", 0, v9 }, +{ "movnz", F3(2, 0x58, 1)|FCC(0)|MCOND(FCONDNZ), MCOND(~FCONDNZ)|FCC(~0)|F3(~2, ~0x58, ~1), "6,I,d", 0, v9 }, +{ "movnz", F3(2, 0x58, 0)|FCC(1)|MCOND(FCONDNZ), MCOND(~FCONDNZ)|FCC(~1)|F3(~2, ~0x58, ~0), "7,2,d", 0, v9 }, +{ "movnz", F3(2, 0x58, 1)|FCC(1)|MCOND(FCONDNZ), MCOND(~FCONDNZ)|FCC(~1)|F3(~2, ~0x58, ~1), "7,I,d", 0, v9 }, +{ "movnz", F3(2, 0x58, 0)|FCC(2)|MCOND(FCONDNZ), MCOND(~FCONDNZ)|FCC(~2)|F3(~2, ~0x58, ~0), "8,2,d", 0, v9 }, +{ "movnz", F3(2, 0x58, 1)|FCC(2)|MCOND(FCONDNZ), MCOND(~FCONDNZ)|FCC(~2)|F3(~2, ~0x58, ~1), "8,I,d", 0, v9 }, +{ "movnz", F3(2, 0x58, 0)|FCC(3)|MCOND(FCONDNZ), MCOND(~FCONDNZ)|FCC(~3)|F3(~2, ~0x58, ~0), "9,2,d", 0, v9 }, +{ "movnz", F3(2, 0x58, 1)|FCC(3)|MCOND(FCONDNZ), MCOND(~FCONDNZ)|FCC(~3)|F3(~2, ~0x58, ~1), "9,I,d", 0, v9 }, +{ "movo", F3(2, 0x58, 0)|FCC(0)|MCOND(FCONDO), MCOND(~FCONDO)|FCC(~0)|F3(~2, ~0x58, ~0), "6,2,d", 0, v9 }, +{ "movo", F3(2, 0x58, 1)|FCC(0)|MCOND(FCONDO), MCOND(~FCONDO)|FCC(~0)|F3(~2, ~0x58, ~1), "6,I,d", 0, v9 }, +{ "movo", F3(2, 0x58, 0)|FCC(1)|MCOND(FCONDO), MCOND(~FCONDO)|FCC(~1)|F3(~2, ~0x58, ~0), "7,2,d", 0, v9 }, +{ "movo", F3(2, 0x58, 1)|FCC(1)|MCOND(FCONDO), MCOND(~FCONDO)|FCC(~1)|F3(~2, ~0x58, ~1), "7,I,d", 0, v9 }, +{ "movo", F3(2, 0x58, 0)|FCC(2)|MCOND(FCONDO), MCOND(~FCONDO)|FCC(~2)|F3(~2, ~0x58, ~0), "8,2,d", 0, v9 }, +{ "movo", F3(2, 0x58, 1)|FCC(2)|MCOND(FCONDO), MCOND(~FCONDO)|FCC(~2)|F3(~2, ~0x58, ~1), "8,I,d", 0, v9 }, +{ "movo", F3(2, 0x58, 0)|FCC(3)|MCOND(FCONDO), MCOND(~FCONDO)|FCC(~3)|F3(~2, ~0x58, ~0), "9,2,d", 0, v9 }, +{ "movo", F3(2, 0x58, 1)|FCC(3)|MCOND(FCONDO), MCOND(~FCONDO)|FCC(~3)|F3(~2, ~0x58, ~1), "9,I,d", 0, v9 }, +{ "movpos", F3(2, 0x59, 0)|MCOND(CONDPOS)|ICC, F3(~2, ~0x59, ~0)|MCOND(~CONDPOS)|XCC|(1<<12), "z,2,d", 0, v9 }, +{ "movpos", F3(2, 0x59, 1)|MCOND(CONDPOS)|ICC, F3(~2, ~0x59, ~1)|MCOND(~CONDPOS)|XCC|(1<<12), "z,I,d", 0, v9 }, +{ "movpos", F3(2, 0x59, 0)|MCOND(CONDPOS)|XCC, F3(~2, ~0x59, ~0)|MCOND(~CONDPOS)|(1<<12), "Z,2,d", 0, v9 }, +{ "movpos", F3(2, 0x59, 1)|MCOND(CONDPOS)|XCC, F3(~2, ~0x59, ~1)|MCOND(~CONDPOS)|(1<<12), "Z,I,d", 0, v9 }, +{ "movu", F3(2, 0x58, 0)|FCC(0)|MCOND(FCONDU), MCOND(~FCONDU)|FCC(~0)|F3(~2, ~0x58, ~0), "6,2,d", 0, v9 }, +{ "movu", F3(2, 0x58, 1)|FCC(0)|MCOND(FCONDU), MCOND(~FCONDU)|FCC(~0)|F3(~2, ~0x58, ~1), "6,I,d", 0, v9 }, +{ "movu", F3(2, 0x58, 0)|FCC(1)|MCOND(FCONDU), MCOND(~FCONDU)|FCC(~1)|F3(~2, ~0x58, ~0), "7,2,d", 0, v9 }, +{ "movu", F3(2, 0x58, 1)|FCC(1)|MCOND(FCONDU), MCOND(~FCONDU)|FCC(~1)|F3(~2, ~0x58, ~1), "7,I,d", 0, v9 }, +{ "movu", F3(2, 0x58, 0)|FCC(2)|MCOND(FCONDU), MCOND(~FCONDU)|FCC(~2)|F3(~2, ~0x58, ~0), "8,2,d", 0, v9 }, +{ "movu", F3(2, 0x58, 1)|FCC(2)|MCOND(FCONDU), MCOND(~FCONDU)|FCC(~2)|F3(~2, ~0x58, ~1), "8,I,d", 0, v9 }, +{ "movu", F3(2, 0x58, 0)|FCC(3)|MCOND(FCONDU), MCOND(~FCONDU)|FCC(~3)|F3(~2, ~0x58, ~0), "9,2,d", 0, v9 }, +{ "movu", F3(2, 0x58, 1)|FCC(3)|MCOND(FCONDU), MCOND(~FCONDU)|FCC(~3)|F3(~2, ~0x58, ~1), "9,I,d", 0, v9 }, +{ "movue", F3(2, 0x58, 0)|FCC(0)|MCOND(FCONDUE), MCOND(~FCONDUE)|FCC(~0)|F3(~2, ~0x58, ~0), "6,2,d", 0, v9 }, +{ "movue", F3(2, 0x58, 1)|FCC(0)|MCOND(FCONDUE), MCOND(~FCONDUE)|FCC(~0)|F3(~2, ~0x58, ~1), "6,I,d", 0, v9 }, +{ "movue", F3(2, 0x58, 0)|FCC(1)|MCOND(FCONDUE), MCOND(~FCONDUE)|FCC(~1)|F3(~2, ~0x58, ~0), "7,2,d", 0, v9 }, +{ "movue", F3(2, 0x58, 1)|FCC(1)|MCOND(FCONDUE), MCOND(~FCONDUE)|FCC(~1)|F3(~2, ~0x58, ~1), "7,I,d", 0, v9 }, +{ "movue", F3(2, 0x58, 0)|FCC(2)|MCOND(FCONDUE), MCOND(~FCONDUE)|FCC(~2)|F3(~2, ~0x58, ~0), "8,2,d", 0, v9 }, +{ "movue", F3(2, 0x58, 1)|FCC(2)|MCOND(FCONDUE), MCOND(~FCONDUE)|FCC(~2)|F3(~2, ~0x58, ~1), "8,I,d", 0, v9 }, +{ "movue", F3(2, 0x58, 0)|FCC(3)|MCOND(FCONDUE), MCOND(~FCONDUE)|FCC(~3)|F3(~2, ~0x58, ~0), "9,2,d", 0, v9 }, +{ "movue", F3(2, 0x58, 1)|FCC(3)|MCOND(FCONDUE), MCOND(~FCONDUE)|FCC(~3)|F3(~2, ~0x58, ~1), "9,I,d", 0, v9 }, +{ "movug", F3(2, 0x58, 0)|FCC(0)|MCOND(FCONDUG), MCOND(~FCONDUG)|FCC(~0)|F3(~2, ~0x58, ~0), "6,2,d", 0, v9 }, +{ "movug", F3(2, 0x58, 1)|FCC(0)|MCOND(FCONDUG), MCOND(~FCONDUG)|FCC(~0)|F3(~2, ~0x58, ~1), "6,I,d", 0, v9 }, +{ "movug", F3(2, 0x58, 0)|FCC(1)|MCOND(FCONDUG), MCOND(~FCONDUG)|FCC(~1)|F3(~2, ~0x58, ~0), "7,2,d", 0, v9 }, +{ "movug", F3(2, 0x58, 1)|FCC(1)|MCOND(FCONDUG), MCOND(~FCONDUG)|FCC(~1)|F3(~2, ~0x58, ~1), "7,I,d", 0, v9 }, +{ "movug", F3(2, 0x58, 0)|FCC(2)|MCOND(FCONDUG), MCOND(~FCONDUG)|FCC(~2)|F3(~2, ~0x58, ~0), "8,2,d", 0, v9 }, +{ "movug", F3(2, 0x58, 1)|FCC(2)|MCOND(FCONDUG), MCOND(~FCONDUG)|FCC(~2)|F3(~2, ~0x58, ~1), "8,I,d", 0, v9 }, +{ "movug", F3(2, 0x58, 0)|FCC(3)|MCOND(FCONDUG), MCOND(~FCONDUG)|FCC(~3)|F3(~2, ~0x58, ~0), "9,2,d", 0, v9 }, +{ "movug", F3(2, 0x58, 1)|FCC(3)|MCOND(FCONDUG), MCOND(~FCONDUG)|FCC(~3)|F3(~2, ~0x58, ~1), "9,I,d", 0, v9 }, +{ "movuge", F3(2, 0x58, 0)|FCC(0)|MCOND(FCONDUGE), MCOND(~FCONDUGE)|FCC(~0)|F3(~2, ~0x58, ~0), "6,2,d", 0, v9 }, +{ "movuge", F3(2, 0x58, 1)|FCC(0)|MCOND(FCONDUGE), MCOND(~FCONDUGE)|FCC(~0)|F3(~2, ~0x58, ~1), "6,I,d", 0, v9 }, +{ "movuge", F3(2, 0x58, 0)|FCC(1)|MCOND(FCONDUGE), MCOND(~FCONDUGE)|FCC(~1)|F3(~2, ~0x58, ~0), "7,2,d", 0, v9 }, +{ "movuge", F3(2, 0x58, 1)|FCC(1)|MCOND(FCONDUGE), MCOND(~FCONDUGE)|FCC(~1)|F3(~2, ~0x58, ~1), "7,I,d", 0, v9 }, +{ "movuge", F3(2, 0x58, 0)|FCC(2)|MCOND(FCONDUGE), MCOND(~FCONDUGE)|FCC(~2)|F3(~2, ~0x58, ~0), "8,2,d", 0, v9 }, +{ "movuge", F3(2, 0x58, 1)|FCC(2)|MCOND(FCONDUGE), MCOND(~FCONDUGE)|FCC(~2)|F3(~2, ~0x58, ~1), "8,I,d", 0, v9 }, +{ "movuge", F3(2, 0x58, 0)|FCC(3)|MCOND(FCONDUGE), MCOND(~FCONDUGE)|FCC(~3)|F3(~2, ~0x58, ~0), "9,2,d", 0, v9 }, +{ "movuge", F3(2, 0x58, 1)|FCC(3)|MCOND(FCONDUGE), MCOND(~FCONDUGE)|FCC(~3)|F3(~2, ~0x58, ~1), "9,I,d", 0, v9 }, +{ "movul", F3(2, 0x58, 0)|FCC(0)|MCOND(FCONDUL), MCOND(~FCONDUL)|FCC(~0)|F3(~2, ~0x58, ~0), "6,2,d", 0, v9 }, +{ "movul", F3(2, 0x58, 1)|FCC(0)|MCOND(FCONDUL), MCOND(~FCONDUL)|FCC(~0)|F3(~2, ~0x58, ~1), "6,I,d", 0, v9 }, +{ "movul", F3(2, 0x58, 0)|FCC(1)|MCOND(FCONDUL), MCOND(~FCONDUL)|FCC(~1)|F3(~2, ~0x58, ~0), "7,2,d", 0, v9 }, +{ "movul", F3(2, 0x58, 1)|FCC(1)|MCOND(FCONDUL), MCOND(~FCONDUL)|FCC(~1)|F3(~2, ~0x58, ~1), "7,I,d", 0, v9 }, +{ "movul", F3(2, 0x58, 0)|FCC(2)|MCOND(FCONDUL), MCOND(~FCONDUL)|FCC(~2)|F3(~2, ~0x58, ~0), "8,2,d", 0, v9 }, +{ "movul", F3(2, 0x58, 1)|FCC(2)|MCOND(FCONDUL), MCOND(~FCONDUL)|FCC(~2)|F3(~2, ~0x58, ~1), "8,I,d", 0, v9 }, +{ "movul", F3(2, 0x58, 0)|FCC(3)|MCOND(FCONDUL), MCOND(~FCONDUL)|FCC(~3)|F3(~2, ~0x58, ~0), "9,2,d", 0, v9 }, +{ "movul", F3(2, 0x58, 1)|FCC(3)|MCOND(FCONDUL), MCOND(~FCONDUL)|FCC(~3)|F3(~2, ~0x58, ~1), "9,I,d", 0, v9 }, +{ "movule", F3(2, 0x58, 0)|FCC(0)|MCOND(FCONDULE), MCOND(~FCONDULE)|FCC(~0)|F3(~2, ~0x58, ~0), "6,2,d", 0, v9 }, +{ "movule", F3(2, 0x58, 1)|FCC(0)|MCOND(FCONDULE), MCOND(~FCONDULE)|FCC(~0)|F3(~2, ~0x58, ~1), "6,I,d", 0, v9 }, +{ "movule", F3(2, 0x58, 0)|FCC(1)|MCOND(FCONDULE), MCOND(~FCONDULE)|FCC(~1)|F3(~2, ~0x58, ~0), "7,2,d", 0, v9 }, +{ "movule", F3(2, 0x58, 1)|FCC(1)|MCOND(FCONDULE), MCOND(~FCONDULE)|FCC(~1)|F3(~2, ~0x58, ~1), "7,I,d", 0, v9 }, +{ "movule", F3(2, 0x58, 0)|FCC(2)|MCOND(FCONDULE), MCOND(~FCONDULE)|FCC(~2)|F3(~2, ~0x58, ~0), "8,2,d", 0, v9 }, +{ "movule", F3(2, 0x58, 1)|FCC(2)|MCOND(FCONDULE), MCOND(~FCONDULE)|FCC(~2)|F3(~2, ~0x58, ~1), "8,I,d", 0, v9 }, +{ "movule", F3(2, 0x58, 0)|FCC(3)|MCOND(FCONDULE), MCOND(~FCONDULE)|FCC(~3)|F3(~2, ~0x58, ~0), "9,2,d", 0, v9 }, +{ "movule", F3(2, 0x58, 1)|FCC(3)|MCOND(FCONDULE), MCOND(~FCONDULE)|FCC(~3)|F3(~2, ~0x58, ~1), "9,I,d", 0, v9 }, +{ "movvc", F3(2, 0x59, 0)|MCOND(CONDVC)|ICC, F3(~2, ~0x59, ~0)|MCOND(~CONDVC)|XCC|(1<<12), "z,2,d", 0, v9 }, +{ "movvc", F3(2, 0x59, 1)|MCOND(CONDVC)|ICC, F3(~2, ~0x59, ~1)|MCOND(~CONDVC)|XCC|(1<<12), "z,I,d", 0, v9 }, +{ "movvc", F3(2, 0x59, 0)|MCOND(CONDVC)|XCC, F3(~2, ~0x59, ~0)|MCOND(~CONDVC)|(1<<12), "Z,2,d", 0, v9 }, +{ "movvc", F3(2, 0x59, 1)|MCOND(CONDVC)|XCC, F3(~2, ~0x59, ~1)|MCOND(~CONDVC)|(1<<12), "Z,I,d", 0, v9 }, +{ "movvs", F3(2, 0x59, 0)|MCOND(CONDVS)|ICC, F3(~2, ~0x59, ~0)|MCOND(~CONDVS)|XCC|(1<<12), "z,2,d", 0, v9 }, +{ "movvs", F3(2, 0x59, 1)|MCOND(CONDVS)|ICC, F3(~2, ~0x59, ~1)|MCOND(~CONDVS)|XCC|(1<<12), "z,I,d", 0, v9 }, +{ "movvs", F3(2, 0x59, 0)|MCOND(CONDVS)|XCC, F3(~2, ~0x59, ~0)|MCOND(~CONDVS)|(1<<12), "Z,2,d", 0, v9 }, +{ "movvs", F3(2, 0x59, 1)|MCOND(CONDVS)|XCC, F3(~2, ~0x59, ~1)|MCOND(~CONDVS)|(1<<12), "Z,I,d", 0, v9 }, +{ "movz", F3(2, 0x58, 0)|FCC(0)|MCOND(FCONDZ), MCOND(~FCONDZ)|FCC(~0)|F3(~2, ~0x58, ~0), "6,2,d", 0, v9 }, +{ "movz", F3(2, 0x58, 1)|FCC(0)|MCOND(FCONDZ), MCOND(~FCONDZ)|FCC(~0)|F3(~2, ~0x58, ~1), "6,I,d", 0, v9 }, +{ "movz", F3(2, 0x58, 0)|FCC(1)|MCOND(FCONDZ), MCOND(~FCONDZ)|FCC(~1)|F3(~2, ~0x58, ~0), "7,2,d", 0, v9 }, +{ "movz", F3(2, 0x58, 1)|FCC(1)|MCOND(FCONDZ), MCOND(~FCONDZ)|FCC(~1)|F3(~2, ~0x58, ~1), "7,I,d", 0, v9 }, +{ "movz", F3(2, 0x58, 0)|FCC(2)|MCOND(FCONDZ), MCOND(~FCONDZ)|FCC(~2)|F3(~2, ~0x58, ~0), "8,2,d", 0, v9 }, +{ "movz", F3(2, 0x58, 1)|FCC(2)|MCOND(FCONDZ), MCOND(~FCONDZ)|FCC(~2)|F3(~2, ~0x58, ~1), "8,I,d", 0, v9 }, +{ "movz", F3(2, 0x58, 0)|FCC(3)|MCOND(FCONDZ), MCOND(~FCONDZ)|FCC(~3)|F3(~2, ~0x58, ~0), "9,2,d", 0, v9 }, +{ "movz", F3(2, 0x58, 1)|FCC(3)|MCOND(FCONDZ), MCOND(~FCONDZ)|FCC(~3)|F3(~2, ~0x58, ~1), "9,I,d", 0, v9 }, + +{ "fmovad", F3F(2, 0x35, 0x082)|MCOND(CONDA), F3F(~2, ~0x35, ~0x082)|MCOND(~CONDA), "z,f,g", 0, v9 }, +{ "fmovad", F3F(2, 0x35, 0x082)|MCOND(FCONDA), F3F(~2, ~0x35, ~0x082)|MCOND(~FCONDA), "6,f,g", 0, v9 }, +{ "fmovad", F3F(2, 0x35, 0x0a2)|MCOND(CONDA), F3F(~2, ~0x35, ~0x0a2)|MCOND(~CONDA), "Z,f,g", 0, v9 }, +{ "fmovad", F3F(2, 0x35, 0x0a2)|MCOND(FCONDA), F3F(~2, ~0x35, ~0x0a2)|MCOND(~FCONDA), "7,f,g", 0, v9 }, +{ "fmovad", F3F(2, 0x35, 0x0c2)|MCOND(FCONDA), F3F(~2, ~0x35, ~0x0c2)|MCOND(~FCONDA), "8,f,g", 0, v9 }, +{ "fmovad", F3F(2, 0x35, 0x0e2)|MCOND(FCONDA), F3F(~2, ~0x35, ~0x0e2)|MCOND(~FCONDA), "9,f,g", 0, v9 }, +{ "fmovaq", F3F(2, 0x35, 0x083)|MCOND(CONDA), F3F(~2, ~0x35, ~0x083)|MCOND(~CONDA), "z,f,g", 0, v9 }, +{ "fmovaq", F3F(2, 0x35, 0x083)|MCOND(FCONDA), F3F(~2, ~0x35, ~0x083)|MCOND(~FCONDA), "6,f,g", 0, v9 }, +{ "fmovaq", F3F(2, 0x35, 0x0a3)|MCOND(CONDA), F3F(~2, ~0x35, ~0x0a3)|MCOND(~CONDA), "Z,f,g", 0, v9 }, +{ "fmovaq", F3F(2, 0x35, 0x0a3)|MCOND(FCONDA), F3F(~2, ~0x35, ~0x0a3)|MCOND(~FCONDA), "7,f,g", 0, v9 }, +{ "fmovaq", F3F(2, 0x35, 0x0c3)|MCOND(FCONDA), F3F(~2, ~0x35, ~0x0c3)|MCOND(~FCONDA), "8,f,g", 0, v9 }, +{ "fmovaq", F3F(2, 0x35, 0x0e3)|MCOND(FCONDA), F3F(~2, ~0x35, ~0x0e3)|MCOND(~FCONDA), "9,f,g", 0, v9 }, +{ "fmovas", F3F(2, 0x35, 0x081)|MCOND(CONDA), F3F(~2, ~0x35, ~0x081)|MCOND(~CONDA), "z,f,g", 0, v9 }, +{ "fmovas", F3F(2, 0x35, 0x081)|MCOND(FCONDA), F3F(~2, ~0x35, ~0x081)|MCOND(~FCONDA), "6,f,g", 0, v9 }, +{ "fmovas", F3F(2, 0x35, 0x0a1)|MCOND(CONDA), F3F(~2, ~0x35, ~0x0a1)|MCOND(~CONDA), "Z,f,g", 0, v9 }, +{ "fmovas", F3F(2, 0x35, 0x0a1)|MCOND(FCONDA), F3F(~2, ~0x35, ~0x0a1)|MCOND(~FCONDA), "7,f,g", 0, v9 }, +{ "fmovas", F3F(2, 0x35, 0x0c1)|MCOND(FCONDA), F3F(~2, ~0x35, ~0x0c1)|MCOND(~FCONDA), "8,f,g", 0, v9 }, +{ "fmovas", F3F(2, 0x35, 0x0e1)|MCOND(FCONDA), F3F(~2, ~0x35, ~0x0e1)|MCOND(~FCONDA), "9,f,g", 0, v9 }, +{ "fmovccd", F3F(2, 0x35, 0x082)|MCOND(CONDCC), F3F(~2, ~0x35, ~0x082)|MCOND(~CONDCC), "z,f,g", 0, v9 }, +{ "fmovccd", F3F(2, 0x35, 0x0a2)|MCOND(CONDCC), F3F(~2, ~0x35, ~0x0a2)|MCOND(~CONDCC), "Z,f,g", 0, v9 }, +{ "fmovccq", F3F(2, 0x35, 0x083)|MCOND(CONDCC), F3F(~2, ~0x35, ~0x083)|MCOND(~CONDCC), "z,f,g", 0, v9 }, +{ "fmovccq", F3F(2, 0x35, 0x0a3)|MCOND(CONDCC), F3F(~2, ~0x35, ~0x0a3)|MCOND(~CONDCC), "Z,f,g", 0, v9 }, +{ "fmovccs", F3F(2, 0x35, 0x081)|MCOND(CONDCC), F3F(~2, ~0x35, ~0x081)|MCOND(~CONDCC), "z,f,g", 0, v9 }, +{ "fmovccs", F3F(2, 0x35, 0x0a1)|MCOND(CONDCC), F3F(~2, ~0x35, ~0x0a1)|MCOND(~CONDCC), "Z,f,g", 0, v9 }, +{ "fmovcsd", F3F(2, 0x35, 0x082)|MCOND(CONDCS), F3F(~2, ~0x35, ~0x082)|MCOND(~CONDCS), "z,f,g", 0, v9 }, +{ "fmovcsd", F3F(2, 0x35, 0x0a2)|MCOND(CONDCS), F3F(~2, ~0x35, ~0x0a2)|MCOND(~CONDCS), "Z,f,g", 0, v9 }, +{ "fmovcsq", F3F(2, 0x35, 0x083)|MCOND(CONDCS), F3F(~2, ~0x35, ~0x083)|MCOND(~CONDCS), "z,f,g", 0, v9 }, +{ "fmovcsq", F3F(2, 0x35, 0x0a3)|MCOND(CONDCS), F3F(~2, ~0x35, ~0x0a3)|MCOND(~CONDCS), "Z,f,g", 0, v9 }, +{ "fmovcss", F3F(2, 0x35, 0x081)|MCOND(CONDCS), F3F(~2, ~0x35, ~0x081)|MCOND(~CONDCS), "z,f,g", 0, v9 }, +{ "fmovcss", F3F(2, 0x35, 0x0a1)|MCOND(CONDCS), F3F(~2, ~0x35, ~0x0a1)|MCOND(~CONDCS), "Z,f,g", 0, v9 }, +{ "fmoved", F3F(2, 0x35, 0x082)|MCOND(CONDE), F3F(~2, ~0x35, ~0x082)|MCOND(~CONDE), "z,f,g", 0, v9 }, +{ "fmoved", F3F(2, 0x35, 0x082)|MCOND(FCONDE), F3F(~2, ~0x35, ~0x082)|MCOND(~FCONDE), "6,f,g", 0, v9 }, +{ "fmoved", F3F(2, 0x35, 0x0a2)|MCOND(CONDE), F3F(~2, ~0x35, ~0x0a2)|MCOND(~CONDE), "Z,f,g", 0, v9 }, +{ "fmoved", F3F(2, 0x35, 0x0a2)|MCOND(FCONDE), F3F(~2, ~0x35, ~0x0a2)|MCOND(~FCONDE), "7,f,g", 0, v9 }, +{ "fmoved", F3F(2, 0x35, 0x0c2)|MCOND(FCONDE), F3F(~2, ~0x35, ~0x0c2)|MCOND(~FCONDE), "8,f,g", 0, v9 }, +{ "fmoved", F3F(2, 0x35, 0x0e2)|MCOND(FCONDE), F3F(~2, ~0x35, ~0x0e2)|MCOND(~FCONDE), "9,f,g", 0, v9 }, +{ "fmoveq", F3F(2, 0x35, 0x083)|MCOND(CONDE), F3F(~2, ~0x35, ~0x083)|MCOND(~CONDE), "z,f,g", 0, v9 }, +{ "fmoveq", F3F(2, 0x35, 0x083)|MCOND(FCONDE), F3F(~2, ~0x35, ~0x083)|MCOND(~FCONDE), "6,f,g", 0, v9 }, +{ "fmoveq", F3F(2, 0x35, 0x0a3)|MCOND(CONDE), F3F(~2, ~0x35, ~0x0a3)|MCOND(~CONDE), "Z,f,g", 0, v9 }, +{ "fmoveq", F3F(2, 0x35, 0x0a3)|MCOND(FCONDE), F3F(~2, ~0x35, ~0x0a3)|MCOND(~FCONDE), "7,f,g", 0, v9 }, +{ "fmoveq", F3F(2, 0x35, 0x0c3)|MCOND(FCONDE), F3F(~2, ~0x35, ~0x0c3)|MCOND(~FCONDE), "8,f,g", 0, v9 }, +{ "fmoveq", F3F(2, 0x35, 0x0e3)|MCOND(FCONDE), F3F(~2, ~0x35, ~0x0e3)|MCOND(~FCONDE), "9,f,g", 0, v9 }, +{ "fmoves", F3F(2, 0x35, 0x081)|MCOND(CONDE), F3F(~2, ~0x35, ~0x081)|MCOND(~CONDE), "z,f,g", 0, v9 }, +{ "fmoves", F3F(2, 0x35, 0x081)|MCOND(FCONDE), F3F(~2, ~0x35, ~0x081)|MCOND(~FCONDE), "6,f,g", 0, v9 }, +{ "fmoves", F3F(2, 0x35, 0x0a1)|MCOND(CONDE), F3F(~2, ~0x35, ~0x0a1)|MCOND(~CONDE), "Z,f,g", 0, v9 }, +{ "fmoves", F3F(2, 0x35, 0x0a1)|MCOND(FCONDE), F3F(~2, ~0x35, ~0x0a1)|MCOND(~FCONDE), "7,f,g", 0, v9 }, +{ "fmoves", F3F(2, 0x35, 0x0c1)|MCOND(FCONDE), F3F(~2, ~0x35, ~0x0c1)|MCOND(~FCONDE), "8,f,g", 0, v9 }, +{ "fmoves", F3F(2, 0x35, 0x0e1)|MCOND(FCONDE), F3F(~2, ~0x35, ~0x0e1)|MCOND(~FCONDE), "9,f,g", 0, v9 }, +{ "fmovgd", F3F(2, 0x35, 0x082)|MCOND(CONDG), F3F(~2, ~0x35, ~0x082)|MCOND(~CONDG), "z,f,g", 0, v9 }, +{ "fmovgd", F3F(2, 0x35, 0x082)|MCOND(FCONDG), F3F(~2, ~0x35, ~0x082)|MCOND(~FCONDG), "6,f,g", 0, v9 }, +{ "fmovgd", F3F(2, 0x35, 0x0a2)|MCOND(CONDG), F3F(~2, ~0x35, ~0x0a2)|MCOND(~CONDG), "Z,f,g", 0, v9 }, +{ "fmovgd", F3F(2, 0x35, 0x0a2)|MCOND(FCONDG), F3F(~2, ~0x35, ~0x0a2)|MCOND(~FCONDG), "7,f,g", 0, v9 }, +{ "fmovgd", F3F(2, 0x35, 0x0c2)|MCOND(FCONDG), F3F(~2, ~0x35, ~0x0c2)|MCOND(~FCONDG), "8,f,g", 0, v9 }, +{ "fmovgd", F3F(2, 0x35, 0x0e2)|MCOND(FCONDG), F3F(~2, ~0x35, ~0x0e2)|MCOND(~FCONDG), "9,f,g", 0, v9 }, +{ "fmovged", F3F(2, 0x35, 0x082)|MCOND(CONDGE), F3F(~2, ~0x35, ~0x082)|MCOND(~CONDGE), "z,f,g", 0, v9 }, +{ "fmovged", F3F(2, 0x35, 0x082)|MCOND(FCONDGE), F3F(~2, ~0x35, ~0x082)|MCOND(~FCONDGE), "6,f,g", 0, v9 }, +{ "fmovged", F3F(2, 0x35, 0x0a2)|MCOND(CONDGE), F3F(~2, ~0x35, ~0x0a2)|MCOND(~CONDGE), "Z,f,g", 0, v9 }, +{ "fmovged", F3F(2, 0x35, 0x0a2)|MCOND(FCONDGE), F3F(~2, ~0x35, ~0x0a2)|MCOND(~FCONDGE), "7,f,g", 0, v9 }, +{ "fmovged", F3F(2, 0x35, 0x0c2)|MCOND(FCONDGE), F3F(~2, ~0x35, ~0x0c2)|MCOND(~FCONDGE), "8,f,g", 0, v9 }, +{ "fmovged", F3F(2, 0x35, 0x0e2)|MCOND(FCONDGE), F3F(~2, ~0x35, ~0x0e2)|MCOND(~FCONDGE), "9,f,g", 0, v9 }, +{ "fmovgeq", F3F(2, 0x35, 0x083)|MCOND(CONDGE), F3F(~2, ~0x35, ~0x083)|MCOND(~CONDGE), "z,f,g", 0, v9 }, +{ "fmovgeq", F3F(2, 0x35, 0x083)|MCOND(FCONDGE), F3F(~2, ~0x35, ~0x083)|MCOND(~FCONDGE), "6,f,g", 0, v9 }, +{ "fmovgeq", F3F(2, 0x35, 0x0a3)|MCOND(CONDGE), F3F(~2, ~0x35, ~0x0a3)|MCOND(~CONDGE), "Z,f,g", 0, v9 }, +{ "fmovgeq", F3F(2, 0x35, 0x0a3)|MCOND(FCONDGE), F3F(~2, ~0x35, ~0x0a3)|MCOND(~FCONDGE), "7,f,g", 0, v9 }, +{ "fmovgeq", F3F(2, 0x35, 0x0c3)|MCOND(FCONDGE), F3F(~2, ~0x35, ~0x0c3)|MCOND(~FCONDGE), "8,f,g", 0, v9 }, +{ "fmovgeq", F3F(2, 0x35, 0x0e3)|MCOND(FCONDGE), F3F(~2, ~0x35, ~0x0e3)|MCOND(~FCONDGE), "9,f,g", 0, v9 }, +{ "fmovges", F3F(2, 0x35, 0x081)|MCOND(CONDGE), F3F(~2, ~0x35, ~0x081)|MCOND(~CONDGE), "z,f,g", 0, v9 }, +{ "fmovges", F3F(2, 0x35, 0x081)|MCOND(FCONDGE), F3F(~2, ~0x35, ~0x081)|MCOND(~FCONDGE), "6,f,g", 0, v9 }, +{ "fmovges", F3F(2, 0x35, 0x0a1)|MCOND(CONDGE), F3F(~2, ~0x35, ~0x0a1)|MCOND(~CONDGE), "Z,f,g", 0, v9 }, +{ "fmovges", F3F(2, 0x35, 0x0a1)|MCOND(FCONDGE), F3F(~2, ~0x35, ~0x0a1)|MCOND(~FCONDGE), "7,f,g", 0, v9 }, +{ "fmovges", F3F(2, 0x35, 0x0c1)|MCOND(FCONDGE), F3F(~2, ~0x35, ~0x0c1)|MCOND(~FCONDGE), "8,f,g", 0, v9 }, +{ "fmovges", F3F(2, 0x35, 0x0e1)|MCOND(FCONDGE), F3F(~2, ~0x35, ~0x0e1)|MCOND(~FCONDGE), "9,f,g", 0, v9 }, +{ "fmovgeud", F3F(2, 0x35, 0x082)|MCOND(CONDGEU), F3F(~2, ~0x35, ~0x082)|MCOND(~CONDGEU), "z,f,g", F_ALIAS, v9 }, +{ "fmovgeud", F3F(2, 0x35, 0x0a2)|MCOND(CONDGEU), F3F(~2, ~0x35, ~0x0a2)|MCOND(~CONDGEU), "Z,f,g", F_ALIAS, v9 }, +{ "fmovgeuq", F3F(2, 0x35, 0x083)|MCOND(CONDGEU), F3F(~2, ~0x35, ~0x083)|MCOND(~CONDGEU), "z,f,g", F_ALIAS, v9 }, +{ "fmovgeuq", F3F(2, 0x35, 0x0a3)|MCOND(CONDGEU), F3F(~2, ~0x35, ~0x0a3)|MCOND(~CONDGEU), "Z,f,g", F_ALIAS, v9 }, +{ "fmovgeus", F3F(2, 0x35, 0x081)|MCOND(CONDGEU), F3F(~2, ~0x35, ~0x081)|MCOND(~CONDGEU), "z,f,g", F_ALIAS, v9 }, +{ "fmovgeus", F3F(2, 0x35, 0x0a1)|MCOND(CONDGEU), F3F(~2, ~0x35, ~0x0a1)|MCOND(~CONDGEU), "Z,f,g", F_ALIAS, v9 }, +{ "fmovgq", F3F(2, 0x35, 0x083)|MCOND(CONDG), F3F(~2, ~0x35, ~0x083)|MCOND(~CONDG), "z,f,g", 0, v9 }, +{ "fmovgq", F3F(2, 0x35, 0x083)|MCOND(FCONDG), F3F(~2, ~0x35, ~0x083)|MCOND(~FCONDG), "6,f,g", 0, v9 }, +{ "fmovgq", F3F(2, 0x35, 0x0a3)|MCOND(CONDG), F3F(~2, ~0x35, ~0x0a3)|MCOND(~CONDG), "Z,f,g", 0, v9 }, +{ "fmovgq", F3F(2, 0x35, 0x0a3)|MCOND(FCONDG), F3F(~2, ~0x35, ~0x0a3)|MCOND(~FCONDG), "7,f,g", 0, v9 }, +{ "fmovgq", F3F(2, 0x35, 0x0c3)|MCOND(FCONDG), F3F(~2, ~0x35, ~0x0c3)|MCOND(~FCONDG), "8,f,g", 0, v9 }, +{ "fmovgq", F3F(2, 0x35, 0x0e3)|MCOND(FCONDG), F3F(~2, ~0x35, ~0x0e3)|MCOND(~FCONDG), "9,f,g", 0, v9 }, +{ "fmovgs", F3F(2, 0x35, 0x081)|MCOND(CONDG), F3F(~2, ~0x35, ~0x081)|MCOND(~CONDG), "z,f,g", 0, v9 }, +{ "fmovgs", F3F(2, 0x35, 0x081)|MCOND(FCONDG), F3F(~2, ~0x35, ~0x081)|MCOND(~FCONDG), "6,f,g", 0, v9 }, +{ "fmovgs", F3F(2, 0x35, 0x0a1)|MCOND(CONDG), F3F(~2, ~0x35, ~0x0a1)|MCOND(~CONDG), "Z,f,g", 0, v9 }, +{ "fmovgs", F3F(2, 0x35, 0x0a1)|MCOND(FCONDG), F3F(~2, ~0x35, ~0x0a1)|MCOND(~FCONDG), "7,f,g", 0, v9 }, +{ "fmovgs", F3F(2, 0x35, 0x0c1)|MCOND(FCONDG), F3F(~2, ~0x35, ~0x0c1)|MCOND(~FCONDG), "8,f,g", 0, v9 }, +{ "fmovgs", F3F(2, 0x35, 0x0e1)|MCOND(FCONDG), F3F(~2, ~0x35, ~0x0e1)|MCOND(~FCONDG), "9,f,g", 0, v9 }, +{ "fmovgud", F3F(2, 0x35, 0x082)|MCOND(CONDGU), F3F(~2, ~0x35, ~0x082)|MCOND(~CONDGU), "z,f,g", 0, v9 }, +{ "fmovgud", F3F(2, 0x35, 0x0a2)|MCOND(CONDGU), F3F(~2, ~0x35, ~0x0a2)|MCOND(~CONDGU), "Z,f,g", 0, v9 }, +{ "fmovguq", F3F(2, 0x35, 0x083)|MCOND(CONDGU), F3F(~2, ~0x35, ~0x083)|MCOND(~CONDGU), "z,f,g", 0, v9 }, +{ "fmovguq", F3F(2, 0x35, 0x0a3)|MCOND(CONDGU), F3F(~2, ~0x35, ~0x0a3)|MCOND(~CONDGU), "Z,f,g", 0, v9 }, +{ "fmovgus", F3F(2, 0x35, 0x081)|MCOND(CONDGU), F3F(~2, ~0x35, ~0x081)|MCOND(~CONDGU), "z,f,g", 0, v9 }, +{ "fmovgus", F3F(2, 0x35, 0x0a1)|MCOND(CONDGU), F3F(~2, ~0x35, ~0x0a1)|MCOND(~CONDGU), "Z,f,g", 0, v9 }, +{ "fmovld", F3F(2, 0x35, 0x082)|MCOND(CONDL), F3F(~2, ~0x35, ~0x082)|MCOND(~CONDL), "z,f,g", 0, v9 }, +{ "fmovld", F3F(2, 0x35, 0x082)|MCOND(FCONDL), F3F(~2, ~0x35, ~0x082)|MCOND(~FCONDL), "6,f,g", 0, v9 }, +{ "fmovld", F3F(2, 0x35, 0x0a2)|MCOND(CONDL), F3F(~2, ~0x35, ~0x0a2)|MCOND(~CONDL), "Z,f,g", 0, v9 }, +{ "fmovld", F3F(2, 0x35, 0x0a2)|MCOND(FCONDL), F3F(~2, ~0x35, ~0x0a2)|MCOND(~FCONDL), "7,f,g", 0, v9 }, +{ "fmovld", F3F(2, 0x35, 0x0c2)|MCOND(FCONDL), F3F(~2, ~0x35, ~0x0c2)|MCOND(~FCONDL), "8,f,g", 0, v9 }, +{ "fmovld", F3F(2, 0x35, 0x0e2)|MCOND(FCONDL), F3F(~2, ~0x35, ~0x0e2)|MCOND(~FCONDL), "9,f,g", 0, v9 }, +{ "fmovled", F3F(2, 0x35, 0x082)|MCOND(CONDLE), F3F(~2, ~0x35, ~0x082)|MCOND(~CONDLE), "z,f,g", 0, v9 }, +{ "fmovled", F3F(2, 0x35, 0x082)|MCOND(FCONDLE), F3F(~2, ~0x35, ~0x082)|MCOND(~FCONDLE), "6,f,g", 0, v9 }, +{ "fmovled", F3F(2, 0x35, 0x0a2)|MCOND(CONDLE), F3F(~2, ~0x35, ~0x0a2)|MCOND(~CONDLE), "Z,f,g", 0, v9 }, +{ "fmovled", F3F(2, 0x35, 0x0a2)|MCOND(FCONDLE), F3F(~2, ~0x35, ~0x0a2)|MCOND(~FCONDLE), "7,f,g", 0, v9 }, +{ "fmovled", F3F(2, 0x35, 0x0c2)|MCOND(FCONDLE), F3F(~2, ~0x35, ~0x0c2)|MCOND(~FCONDLE), "8,f,g", 0, v9 }, +{ "fmovled", F3F(2, 0x35, 0x0e2)|MCOND(FCONDLE), F3F(~2, ~0x35, ~0x0e2)|MCOND(~FCONDLE), "9,f,g", 0, v9 }, +{ "fmovleq", F3F(2, 0x35, 0x083)|MCOND(CONDLE), F3F(~2, ~0x35, ~0x083)|MCOND(~CONDLE), "z,f,g", 0, v9 }, +{ "fmovleq", F3F(2, 0x35, 0x083)|MCOND(FCONDLE), F3F(~2, ~0x35, ~0x083)|MCOND(~FCONDLE), "6,f,g", 0, v9 }, +{ "fmovleq", F3F(2, 0x35, 0x0a3)|MCOND(CONDLE), F3F(~2, ~0x35, ~0x0a3)|MCOND(~CONDLE), "Z,f,g", 0, v9 }, +{ "fmovleq", F3F(2, 0x35, 0x0a3)|MCOND(FCONDLE), F3F(~2, ~0x35, ~0x0a3)|MCOND(~FCONDLE), "7,f,g", 0, v9 }, +{ "fmovleq", F3F(2, 0x35, 0x0c3)|MCOND(FCONDLE), F3F(~2, ~0x35, ~0x0c3)|MCOND(~FCONDLE), "8,f,g", 0, v9 }, +{ "fmovleq", F3F(2, 0x35, 0x0e3)|MCOND(FCONDLE), F3F(~2, ~0x35, ~0x0e3)|MCOND(~FCONDLE), "9,f,g", 0, v9 }, +{ "fmovles", F3F(2, 0x35, 0x081)|MCOND(CONDLE), F3F(~2, ~0x35, ~0x081)|MCOND(~CONDLE), "z,f,g", 0, v9 }, +{ "fmovles", F3F(2, 0x35, 0x081)|MCOND(FCONDLE), F3F(~2, ~0x35, ~0x081)|MCOND(~FCONDLE), "6,f,g", 0, v9 }, +{ "fmovles", F3F(2, 0x35, 0x0a1)|MCOND(CONDLE), F3F(~2, ~0x35, ~0x0a1)|MCOND(~CONDLE), "Z,f,g", 0, v9 }, +{ "fmovles", F3F(2, 0x35, 0x0a1)|MCOND(FCONDLE), F3F(~2, ~0x35, ~0x0a1)|MCOND(~FCONDLE), "7,f,g", 0, v9 }, +{ "fmovles", F3F(2, 0x35, 0x0c1)|MCOND(FCONDLE), F3F(~2, ~0x35, ~0x0c1)|MCOND(~FCONDLE), "8,f,g", 0, v9 }, +{ "fmovles", F3F(2, 0x35, 0x0e1)|MCOND(FCONDLE), F3F(~2, ~0x35, ~0x0e1)|MCOND(~FCONDLE), "9,f,g", 0, v9 }, +{ "fmovleud", F3F(2, 0x35, 0x082)|MCOND(CONDLEU), F3F(~2, ~0x35, ~0x082)|MCOND(~CONDLEU), "z,f,g", 0, v9 }, +{ "fmovleud", F3F(2, 0x35, 0x0a2)|MCOND(CONDLEU), F3F(~2, ~0x35, ~0x0a2)|MCOND(~CONDLEU), "Z,f,g", 0, v9 }, +{ "fmovleuq", F3F(2, 0x35, 0x083)|MCOND(CONDLEU), F3F(~2, ~0x35, ~0x083)|MCOND(~CONDLEU), "z,f,g", 0, v9 }, +{ "fmovleuq", F3F(2, 0x35, 0x0a3)|MCOND(CONDLEU), F3F(~2, ~0x35, ~0x0a3)|MCOND(~CONDLEU), "Z,f,g", 0, v9 }, +{ "fmovleus", F3F(2, 0x35, 0x081)|MCOND(CONDLEU), F3F(~2, ~0x35, ~0x081)|MCOND(~CONDLEU), "z,f,g", 0, v9 }, +{ "fmovleus", F3F(2, 0x35, 0x0a1)|MCOND(CONDLEU), F3F(~2, ~0x35, ~0x0a1)|MCOND(~CONDLEU), "Z,f,g", 0, v9 }, +{ "fmovlgd", F3F(2, 0x35, 0x082)|MCOND(FCONDLG), F3F(~2, ~0x35, ~0x082)|MCOND(~FCONDLG), "6,f,g", 0, v9 }, +{ "fmovlgd", F3F(2, 0x35, 0x0a2)|MCOND(FCONDLG), F3F(~2, ~0x35, ~0x0a2)|MCOND(~FCONDLG), "7,f,g", 0, v9 }, +{ "fmovlgd", F3F(2, 0x35, 0x0c2)|MCOND(FCONDLG), F3F(~2, ~0x35, ~0x0c2)|MCOND(~FCONDLG), "8,f,g", 0, v9 }, +{ "fmovlgd", F3F(2, 0x35, 0x0e2)|MCOND(FCONDLG), F3F(~2, ~0x35, ~0x0e2)|MCOND(~FCONDLG), "9,f,g", 0, v9 }, +{ "fmovlgq", F3F(2, 0x35, 0x083)|MCOND(FCONDLG), F3F(~2, ~0x35, ~0x083)|MCOND(~FCONDLG), "6,f,g", 0, v9 }, +{ "fmovlgq", F3F(2, 0x35, 0x0a3)|MCOND(FCONDLG), F3F(~2, ~0x35, ~0x0a3)|MCOND(~FCONDLG), "7,f,g", 0, v9 }, +{ "fmovlgq", F3F(2, 0x35, 0x0c3)|MCOND(FCONDLG), F3F(~2, ~0x35, ~0x0c3)|MCOND(~FCONDLG), "8,f,g", 0, v9 }, +{ "fmovlgq", F3F(2, 0x35, 0x0e3)|MCOND(FCONDLG), F3F(~2, ~0x35, ~0x0e3)|MCOND(~FCONDLG), "9,f,g", 0, v9 }, +{ "fmovlgs", F3F(2, 0x35, 0x081)|MCOND(FCONDLG), F3F(~2, ~0x35, ~0x081)|MCOND(~FCONDLG), "6,f,g", 0, v9 }, +{ "fmovlgs", F3F(2, 0x35, 0x0a1)|MCOND(FCONDLG), F3F(~2, ~0x35, ~0x0a1)|MCOND(~FCONDLG), "7,f,g", 0, v9 }, +{ "fmovlgs", F3F(2, 0x35, 0x0c1)|MCOND(FCONDLG), F3F(~2, ~0x35, ~0x0c1)|MCOND(~FCONDLG), "8,f,g", 0, v9 }, +{ "fmovlgs", F3F(2, 0x35, 0x0e1)|MCOND(FCONDLG), F3F(~2, ~0x35, ~0x0e1)|MCOND(~FCONDLG), "9,f,g", 0, v9 }, +{ "fmovlq", F3F(2, 0x35, 0x083)|MCOND(CONDL), F3F(~2, ~0x35, ~0x083)|MCOND(~CONDL), "z,f,g", 0, v9 }, +{ "fmovlq", F3F(2, 0x35, 0x083)|MCOND(FCONDL), F3F(~2, ~0x35, ~0x083)|MCOND(~FCONDL), "6,f,g", 0, v9 }, +{ "fmovlq", F3F(2, 0x35, 0x0a3)|MCOND(CONDL), F3F(~2, ~0x35, ~0x0a3)|MCOND(~CONDL), "Z,f,g", 0, v9 }, +{ "fmovlq", F3F(2, 0x35, 0x0a3)|MCOND(FCONDL), F3F(~2, ~0x35, ~0x0a3)|MCOND(~FCONDL), "7,f,g", 0, v9 }, +{ "fmovlq", F3F(2, 0x35, 0x0c3)|MCOND(FCONDL), F3F(~2, ~0x35, ~0x0c3)|MCOND(~FCONDL), "8,f,g", 0, v9 }, +{ "fmovlq", F3F(2, 0x35, 0x0e3)|MCOND(FCONDL), F3F(~2, ~0x35, ~0x0e3)|MCOND(~FCONDL), "9,f,g", 0, v9 }, +{ "fmovls", F3F(2, 0x35, 0x081)|MCOND(CONDL), F3F(~2, ~0x35, ~0x081)|MCOND(~CONDL), "z,f,g", 0, v9 }, +{ "fmovls", F3F(2, 0x35, 0x081)|MCOND(FCONDL), F3F(~2, ~0x35, ~0x081)|MCOND(~FCONDL), "6,f,g", 0, v9 }, +{ "fmovls", F3F(2, 0x35, 0x0a1)|MCOND(CONDL), F3F(~2, ~0x35, ~0x0a1)|MCOND(~CONDL), "Z,f,g", 0, v9 }, +{ "fmovls", F3F(2, 0x35, 0x0a1)|MCOND(FCONDL), F3F(~2, ~0x35, ~0x0a1)|MCOND(~FCONDL), "7,f,g", 0, v9 }, +{ "fmovls", F3F(2, 0x35, 0x0c1)|MCOND(FCONDL), F3F(~2, ~0x35, ~0x0c1)|MCOND(~FCONDL), "8,f,g", 0, v9 }, +{ "fmovls", F3F(2, 0x35, 0x0e1)|MCOND(FCONDL), F3F(~2, ~0x35, ~0x0e1)|MCOND(~FCONDL), "9,f,g", 0, v9 }, +{ "fmovlud", F3F(2, 0x35, 0x082)|MCOND(CONDLU), F3F(~2, ~0x35, ~0x082)|MCOND(~CONDLU), "z,f,g", F_ALIAS, v9 }, +{ "fmovlud", F3F(2, 0x35, 0x0a2)|MCOND(CONDLU), F3F(~2, ~0x35, ~0x0a2)|MCOND(~CONDLU), "Z,f,g", F_ALIAS, v9 }, +{ "fmovluq", F3F(2, 0x35, 0x083)|MCOND(CONDLU), F3F(~2, ~0x35, ~0x083)|MCOND(~CONDLU), "z,f,g", F_ALIAS, v9 }, +{ "fmovluq", F3F(2, 0x35, 0x0a3)|MCOND(CONDLU), F3F(~2, ~0x35, ~0x0a3)|MCOND(~CONDLU), "Z,f,g", F_ALIAS, v9 }, +{ "fmovlus", F3F(2, 0x35, 0x081)|MCOND(CONDLU), F3F(~2, ~0x35, ~0x081)|MCOND(~CONDLU), "z,f,g", F_ALIAS, v9 }, +{ "fmovlus", F3F(2, 0x35, 0x0a1)|MCOND(CONDLU), F3F(~2, ~0x35, ~0x0a1)|MCOND(~CONDLU), "Z,f,g", F_ALIAS, v9 }, +{ "fmovnd", F3F(2, 0x35, 0x082)|MCOND(CONDN), F3F(~2, ~0x35, ~0x082)|MCOND(~CONDN), "z,f,g", 0, v9 }, +{ "fmovnd", F3F(2, 0x35, 0x082)|MCOND(FCONDN), F3F(~2, ~0x35, ~0x082)|MCOND(~FCONDN), "6,f,g", 0, v9 }, +{ "fmovnd", F3F(2, 0x35, 0x0a2)|MCOND(CONDN), F3F(~2, ~0x35, ~0x0a2)|MCOND(~CONDN), "Z,f,g", 0, v9 }, +{ "fmovnd", F3F(2, 0x35, 0x0a2)|MCOND(FCONDN), F3F(~2, ~0x35, ~0x0a2)|MCOND(~FCONDN), "7,f,g", 0, v9 }, +{ "fmovnd", F3F(2, 0x35, 0x0c2)|MCOND(FCONDN), F3F(~2, ~0x35, ~0x0c2)|MCOND(~FCONDN), "8,f,g", 0, v9 }, +{ "fmovnd", F3F(2, 0x35, 0x0e2)|MCOND(FCONDN), F3F(~2, ~0x35, ~0x0e2)|MCOND(~FCONDN), "9,f,g", 0, v9 }, +{ "fmovned", F3F(2, 0x35, 0x082)|MCOND(CONDNE), F3F(~2, ~0x35, ~0x082)|MCOND(~CONDNE), "z,f,g", 0, v9 }, +{ "fmovned", F3F(2, 0x35, 0x082)|MCOND(FCONDNE), F3F(~2, ~0x35, ~0x082)|MCOND(~FCONDNE), "6,f,g", 0, v9 }, +{ "fmovned", F3F(2, 0x35, 0x0a2)|MCOND(CONDNE), F3F(~2, ~0x35, ~0x0a2)|MCOND(~CONDNE), "Z,f,g", 0, v9 }, +{ "fmovned", F3F(2, 0x35, 0x0a2)|MCOND(FCONDNE), F3F(~2, ~0x35, ~0x0a2)|MCOND(~FCONDNE), "7,f,g", 0, v9 }, +{ "fmovned", F3F(2, 0x35, 0x0c2)|MCOND(FCONDNE), F3F(~2, ~0x35, ~0x0c2)|MCOND(~FCONDNE), "8,f,g", 0, v9 }, +{ "fmovned", F3F(2, 0x35, 0x0e2)|MCOND(FCONDNE), F3F(~2, ~0x35, ~0x0e2)|MCOND(~FCONDNE), "9,f,g", 0, v9 }, +{ "fmovnegd", F3F(2, 0x35, 0x082)|MCOND(CONDNEG), F3F(~2, ~0x35, ~0x082)|MCOND(~CONDNEG), "z,f,g", 0, v9 }, +{ "fmovnegd", F3F(2, 0x35, 0x0a2)|MCOND(CONDNEG), F3F(~2, ~0x35, ~0x0a2)|MCOND(~CONDNEG), "Z,f,g", 0, v9 }, +{ "fmovnegq", F3F(2, 0x35, 0x083)|MCOND(CONDNEG), F3F(~2, ~0x35, ~0x083)|MCOND(~CONDNEG), "z,f,g", 0, v9 }, +{ "fmovnegq", F3F(2, 0x35, 0x0a3)|MCOND(CONDNEG), F3F(~2, ~0x35, ~0x0a3)|MCOND(~CONDNEG), "Z,f,g", 0, v9 }, +{ "fmovnegs", F3F(2, 0x35, 0x081)|MCOND(CONDNEG), F3F(~2, ~0x35, ~0x081)|MCOND(~CONDNEG), "z,f,g", 0, v9 }, +{ "fmovnegs", F3F(2, 0x35, 0x0a1)|MCOND(CONDNEG), F3F(~2, ~0x35, ~0x0a1)|MCOND(~CONDNEG), "Z,f,g", 0, v9 }, +{ "fmovneq", F3F(2, 0x35, 0x083)|MCOND(CONDNE), F3F(~2, ~0x35, ~0x083)|MCOND(~CONDNE), "z,f,g", 0, v9 }, +{ "fmovneq", F3F(2, 0x35, 0x083)|MCOND(FCONDNE), F3F(~2, ~0x35, ~0x083)|MCOND(~FCONDNE), "6,f,g", 0, v9 }, +{ "fmovneq", F3F(2, 0x35, 0x0a3)|MCOND(CONDNE), F3F(~2, ~0x35, ~0x0a3)|MCOND(~CONDNE), "Z,f,g", 0, v9 }, +{ "fmovneq", F3F(2, 0x35, 0x0a3)|MCOND(FCONDNE), F3F(~2, ~0x35, ~0x0a3)|MCOND(~FCONDNE), "7,f,g", 0, v9 }, +{ "fmovneq", F3F(2, 0x35, 0x0c3)|MCOND(FCONDNE), F3F(~2, ~0x35, ~0x0c3)|MCOND(~FCONDNE), "8,f,g", 0, v9 }, +{ "fmovneq", F3F(2, 0x35, 0x0e3)|MCOND(FCONDNE), F3F(~2, ~0x35, ~0x0e3)|MCOND(~FCONDNE), "9,f,g", 0, v9 }, +{ "fmovnes", F3F(2, 0x35, 0x081)|MCOND(CONDNE), F3F(~2, ~0x35, ~0x081)|MCOND(~CONDNE), "z,f,g", 0, v9 }, +{ "fmovnes", F3F(2, 0x35, 0x081)|MCOND(FCONDNE), F3F(~2, ~0x35, ~0x081)|MCOND(~FCONDNE), "6,f,g", 0, v9 }, +{ "fmovnes", F3F(2, 0x35, 0x0a1)|MCOND(CONDNE), F3F(~2, ~0x35, ~0x0a1)|MCOND(~CONDNE), "Z,f,g", 0, v9 }, +{ "fmovnes", F3F(2, 0x35, 0x0a1)|MCOND(FCONDNE), F3F(~2, ~0x35, ~0x0a1)|MCOND(~FCONDNE), "7,f,g", 0, v9 }, +{ "fmovnes", F3F(2, 0x35, 0x0c1)|MCOND(FCONDNE), F3F(~2, ~0x35, ~0x0c1)|MCOND(~FCONDNE), "8,f,g", 0, v9 }, +{ "fmovnes", F3F(2, 0x35, 0x0e1)|MCOND(FCONDNE), F3F(~2, ~0x35, ~0x0e1)|MCOND(~FCONDNE), "9,f,g", 0, v9 }, +{ "fmovnq", F3F(2, 0x35, 0x083)|MCOND(CONDN), F3F(~2, ~0x35, ~0x083)|MCOND(~CONDN), "z,f,g", 0, v9 }, +{ "fmovnq", F3F(2, 0x35, 0x083)|MCOND(FCONDN), F3F(~2, ~0x35, ~0x083)|MCOND(~FCONDN), "6,f,g", 0, v9 }, +{ "fmovnq", F3F(2, 0x35, 0x0a3)|MCOND(CONDN), F3F(~2, ~0x35, ~0x0a3)|MCOND(~CONDN), "Z,f,g", 0, v9 }, +{ "fmovnq", F3F(2, 0x35, 0x0a3)|MCOND(FCONDN), F3F(~2, ~0x35, ~0x0a3)|MCOND(~FCONDN), "7,f,g", 0, v9 }, +{ "fmovnq", F3F(2, 0x35, 0x0c3)|MCOND(FCONDN), F3F(~2, ~0x35, ~0x0c3)|MCOND(~FCONDN), "8,f,g", 0, v9 }, +{ "fmovnq", F3F(2, 0x35, 0x0e3)|MCOND(FCONDN), F3F(~2, ~0x35, ~0x0e3)|MCOND(~FCONDN), "9,f,g", 0, v9 }, +{ "fmovns", F3F(2, 0x35, 0x081)|MCOND(CONDN), F3F(~2, ~0x35, ~0x081)|MCOND(~CONDN), "z,f,g", 0, v9 }, +{ "fmovns", F3F(2, 0x35, 0x081)|MCOND(FCONDN), F3F(~2, ~0x35, ~0x081)|MCOND(~FCONDN), "6,f,g", 0, v9 }, +{ "fmovns", F3F(2, 0x35, 0x0a1)|MCOND(CONDN), F3F(~2, ~0x35, ~0x0a1)|MCOND(~CONDN), "Z,f,g", 0, v9 }, +{ "fmovns", F3F(2, 0x35, 0x0a1)|MCOND(FCONDN), F3F(~2, ~0x35, ~0x0a1)|MCOND(~FCONDN), "7,f,g", 0, v9 }, +{ "fmovns", F3F(2, 0x35, 0x0c1)|MCOND(FCONDN), F3F(~2, ~0x35, ~0x0c1)|MCOND(~FCONDN), "8,f,g", 0, v9 }, +{ "fmovns", F3F(2, 0x35, 0x0e1)|MCOND(FCONDN), F3F(~2, ~0x35, ~0x0e1)|MCOND(~FCONDN), "9,f,g", 0, v9 }, +{ "fmovnzd", F3F(2, 0x35, 0x082)|MCOND(CONDNZ), F3F(~2, ~0x35, ~0x082)|MCOND(~CONDNZ), "z,f,g", F_ALIAS, v9 }, +{ "fmovnzd", F3F(2, 0x35, 0x082)|MCOND(FCONDNZ), F3F(~2, ~0x35, ~0x082)|MCOND(~FCONDNZ), "6,f,g", F_ALIAS, v9 }, +{ "fmovnzd", F3F(2, 0x35, 0x0a2)|MCOND(CONDNZ), F3F(~2, ~0x35, ~0x0a2)|MCOND(~CONDNZ), "Z,f,g", F_ALIAS, v9 }, +{ "fmovnzd", F3F(2, 0x35, 0x0a2)|MCOND(FCONDNZ), F3F(~2, ~0x35, ~0x0a2)|MCOND(~FCONDNZ), "7,f,g", F_ALIAS, v9 }, +{ "fmovnzd", F3F(2, 0x35, 0x0c2)|MCOND(FCONDNZ), F3F(~2, ~0x35, ~0x0c2)|MCOND(~FCONDNZ), "8,f,g", F_ALIAS, v9 }, +{ "fmovnzd", F3F(2, 0x35, 0x0e2)|MCOND(FCONDNZ), F3F(~2, ~0x35, ~0x0e2)|MCOND(~FCONDNZ), "9,f,g", F_ALIAS, v9 }, +{ "fmovnzq", F3F(2, 0x35, 0x083)|MCOND(CONDNZ), F3F(~2, ~0x35, ~0x083)|MCOND(~CONDNZ), "z,f,g", F_ALIAS, v9 }, +{ "fmovnzq", F3F(2, 0x35, 0x083)|MCOND(FCONDNZ), F3F(~2, ~0x35, ~0x083)|MCOND(~FCONDNZ), "6,f,g", F_ALIAS, v9 }, +{ "fmovnzq", F3F(2, 0x35, 0x0a3)|MCOND(CONDNZ), F3F(~2, ~0x35, ~0x0a3)|MCOND(~CONDNZ), "Z,f,g", F_ALIAS, v9 }, +{ "fmovnzq", F3F(2, 0x35, 0x0a3)|MCOND(FCONDNZ), F3F(~2, ~0x35, ~0x0a3)|MCOND(~FCONDNZ), "7,f,g", F_ALIAS, v9 }, +{ "fmovnzq", F3F(2, 0x35, 0x0c3)|MCOND(FCONDNZ), F3F(~2, ~0x35, ~0x0c3)|MCOND(~FCONDNZ), "8,f,g", F_ALIAS, v9 }, +{ "fmovnzq", F3F(2, 0x35, 0x0e3)|MCOND(FCONDNZ), F3F(~2, ~0x35, ~0x0e3)|MCOND(~FCONDNZ), "9,f,g", F_ALIAS, v9 }, +{ "fmovnzs", F3F(2, 0x35, 0x081)|MCOND(CONDNZ), F3F(~2, ~0x35, ~0x081)|MCOND(~CONDNZ), "z,f,g", F_ALIAS, v9 }, +{ "fmovnzs", F3F(2, 0x35, 0x081)|MCOND(FCONDNZ), F3F(~2, ~0x35, ~0x081)|MCOND(~FCONDNZ), "6,f,g", F_ALIAS, v9 }, +{ "fmovnzs", F3F(2, 0x35, 0x0a1)|MCOND(CONDNZ), F3F(~2, ~0x35, ~0x0a1)|MCOND(~CONDNZ), "Z,f,g", F_ALIAS, v9 }, +{ "fmovnzs", F3F(2, 0x35, 0x0a1)|MCOND(FCONDNZ), F3F(~2, ~0x35, ~0x0a1)|MCOND(~FCONDNZ), "7,f,g", F_ALIAS, v9 }, +{ "fmovnzs", F3F(2, 0x35, 0x0c1)|MCOND(FCONDNZ), F3F(~2, ~0x35, ~0x0c1)|MCOND(~FCONDNZ), "8,f,g", F_ALIAS, v9 }, +{ "fmovnzs", F3F(2, 0x35, 0x0e1)|MCOND(FCONDNZ), F3F(~2, ~0x35, ~0x0e1)|MCOND(~FCONDNZ), "9,f,g", F_ALIAS, v9 }, +{ "fmovod", F3F(2, 0x35, 0x082)|MCOND(FCONDO), F3F(~2, ~0x35, ~0x082)|MCOND(~FCONDO), "6,f,g", 0, v9 }, +{ "fmovod", F3F(2, 0x35, 0x0a2)|MCOND(FCONDO), F3F(~2, ~0x35, ~0x0a2)|MCOND(~FCONDO), "7,f,g", 0, v9 }, +{ "fmovod", F3F(2, 0x35, 0x0c2)|MCOND(FCONDO), F3F(~2, ~0x35, ~0x0c2)|MCOND(~FCONDO), "8,f,g", 0, v9 }, +{ "fmovod", F3F(2, 0x35, 0x0e2)|MCOND(FCONDO), F3F(~2, ~0x35, ~0x0e2)|MCOND(~FCONDO), "9,f,g", 0, v9 }, +{ "fmovoq", F3F(2, 0x35, 0x083)|MCOND(FCONDO), F3F(~2, ~0x35, ~0x083)|MCOND(~FCONDO), "6,f,g", 0, v9 }, +{ "fmovoq", F3F(2, 0x35, 0x0a3)|MCOND(FCONDO), F3F(~2, ~0x35, ~0x0a3)|MCOND(~FCONDO), "7,f,g", 0, v9 }, +{ "fmovoq", F3F(2, 0x35, 0x0c3)|MCOND(FCONDO), F3F(~2, ~0x35, ~0x0c3)|MCOND(~FCONDO), "8,f,g", 0, v9 }, +{ "fmovoq", F3F(2, 0x35, 0x0e3)|MCOND(FCONDO), F3F(~2, ~0x35, ~0x0e3)|MCOND(~FCONDO), "9,f,g", 0, v9 }, +{ "fmovos", F3F(2, 0x35, 0x081)|MCOND(FCONDO), F3F(~2, ~0x35, ~0x081)|MCOND(~FCONDO), "6,f,g", 0, v9 }, +{ "fmovos", F3F(2, 0x35, 0x0a1)|MCOND(FCONDO), F3F(~2, ~0x35, ~0x0a1)|MCOND(~FCONDO), "7,f,g", 0, v9 }, +{ "fmovos", F3F(2, 0x35, 0x0c1)|MCOND(FCONDO), F3F(~2, ~0x35, ~0x0c1)|MCOND(~FCONDO), "8,f,g", 0, v9 }, +{ "fmovos", F3F(2, 0x35, 0x0e1)|MCOND(FCONDO), F3F(~2, ~0x35, ~0x0e1)|MCOND(~FCONDO), "9,f,g", 0, v9 }, +{ "fmovposd", F3F(2, 0x35, 0x082)|MCOND(CONDPOS), F3F(~2, ~0x35, ~0x082)|MCOND(~CONDPOS), "z,f,g", 0, v9 }, +{ "fmovposd", F3F(2, 0x35, 0x0a2)|MCOND(CONDPOS), F3F(~2, ~0x35, ~0x0a2)|MCOND(~CONDPOS), "Z,f,g", 0, v9 }, +{ "fmovposq", F3F(2, 0x35, 0x083)|MCOND(CONDPOS), F3F(~2, ~0x35, ~0x083)|MCOND(~CONDPOS), "z,f,g", 0, v9 }, +{ "fmovposq", F3F(2, 0x35, 0x0a3)|MCOND(CONDPOS), F3F(~2, ~0x35, ~0x0a3)|MCOND(~CONDPOS), "Z,f,g", 0, v9 }, +{ "fmovposs", F3F(2, 0x35, 0x081)|MCOND(CONDPOS), F3F(~2, ~0x35, ~0x081)|MCOND(~CONDPOS), "z,f,g", 0, v9 }, +{ "fmovposs", F3F(2, 0x35, 0x0a1)|MCOND(CONDPOS), F3F(~2, ~0x35, ~0x0a1)|MCOND(~CONDPOS), "Z,f,g", 0, v9 }, +{ "fmovud", F3F(2, 0x35, 0x082)|MCOND(FCONDU), F3F(~2, ~0x35, ~0x082)|MCOND(~FCONDU), "6,f,g", 0, v9 }, +{ "fmovud", F3F(2, 0x35, 0x0a2)|MCOND(FCONDU), F3F(~2, ~0x35, ~0x0a2)|MCOND(~FCONDU), "7,f,g", 0, v9 }, +{ "fmovud", F3F(2, 0x35, 0x0c2)|MCOND(FCONDU), F3F(~2, ~0x35, ~0x0c2)|MCOND(~FCONDU), "8,f,g", 0, v9 }, +{ "fmovud", F3F(2, 0x35, 0x0e2)|MCOND(FCONDU), F3F(~2, ~0x35, ~0x0e2)|MCOND(~FCONDU), "9,f,g", 0, v9 }, +{ "fmovued", F3F(2, 0x35, 0x082)|MCOND(FCONDUE), F3F(~2, ~0x35, ~0x082)|MCOND(~FCONDUE), "6,f,g", 0, v9 }, +{ "fmovued", F3F(2, 0x35, 0x0a2)|MCOND(FCONDUE), F3F(~2, ~0x35, ~0x0a2)|MCOND(~FCONDUE), "7,f,g", 0, v9 }, +{ "fmovued", F3F(2, 0x35, 0x0c2)|MCOND(FCONDUE), F3F(~2, ~0x35, ~0x0c2)|MCOND(~FCONDUE), "8,f,g", 0, v9 }, +{ "fmovued", F3F(2, 0x35, 0x0e2)|MCOND(FCONDUE), F3F(~2, ~0x35, ~0x0e2)|MCOND(~FCONDUE), "9,f,g", 0, v9 }, +{ "fmovueq", F3F(2, 0x35, 0x083)|MCOND(FCONDUE), F3F(~2, ~0x35, ~0x083)|MCOND(~FCONDUE), "6,f,g", 0, v9 }, +{ "fmovueq", F3F(2, 0x35, 0x0a3)|MCOND(FCONDUE), F3F(~2, ~0x35, ~0x0a3)|MCOND(~FCONDUE), "7,f,g", 0, v9 }, +{ "fmovueq", F3F(2, 0x35, 0x0c3)|MCOND(FCONDUE), F3F(~2, ~0x35, ~0x0c3)|MCOND(~FCONDUE), "8,f,g", 0, v9 }, +{ "fmovueq", F3F(2, 0x35, 0x0e3)|MCOND(FCONDUE), F3F(~2, ~0x35, ~0x0e3)|MCOND(~FCONDUE), "9,f,g", 0, v9 }, +{ "fmovues", F3F(2, 0x35, 0x081)|MCOND(FCONDUE), F3F(~2, ~0x35, ~0x081)|MCOND(~FCONDUE), "6,f,g", 0, v9 }, +{ "fmovues", F3F(2, 0x35, 0x0a1)|MCOND(FCONDUE), F3F(~2, ~0x35, ~0x0a1)|MCOND(~FCONDUE), "7,f,g", 0, v9 }, +{ "fmovues", F3F(2, 0x35, 0x0c1)|MCOND(FCONDUE), F3F(~2, ~0x35, ~0x0c1)|MCOND(~FCONDUE), "8,f,g", 0, v9 }, +{ "fmovues", F3F(2, 0x35, 0x0e1)|MCOND(FCONDUE), F3F(~2, ~0x35, ~0x0e1)|MCOND(~FCONDUE), "9,f,g", 0, v9 }, +{ "fmovugd", F3F(2, 0x35, 0x082)|MCOND(FCONDUG), F3F(~2, ~0x35, ~0x082)|MCOND(~FCONDUG), "6,f,g", 0, v9 }, +{ "fmovugd", F3F(2, 0x35, 0x0a2)|MCOND(FCONDUG), F3F(~2, ~0x35, ~0x0a2)|MCOND(~FCONDUG), "7,f,g", 0, v9 }, +{ "fmovugd", F3F(2, 0x35, 0x0c2)|MCOND(FCONDUG), F3F(~2, ~0x35, ~0x0c2)|MCOND(~FCONDUG), "8,f,g", 0, v9 }, +{ "fmovugd", F3F(2, 0x35, 0x0e2)|MCOND(FCONDUG), F3F(~2, ~0x35, ~0x0e2)|MCOND(~FCONDUG), "9,f,g", 0, v9 }, +{ "fmovuged", F3F(2, 0x35, 0x082)|MCOND(FCONDUGE), F3F(~2, ~0x35, ~0x082)|MCOND(~FCONDUGE), "6,f,g", 0, v9 }, +{ "fmovuged", F3F(2, 0x35, 0x0a2)|MCOND(FCONDUGE), F3F(~2, ~0x35, ~0x0a2)|MCOND(~FCONDUGE), "7,f,g", 0, v9 }, +{ "fmovuged", F3F(2, 0x35, 0x0c2)|MCOND(FCONDUGE), F3F(~2, ~0x35, ~0x0c2)|MCOND(~FCONDUGE), "8,f,g", 0, v9 }, +{ "fmovuged", F3F(2, 0x35, 0x0e2)|MCOND(FCONDUGE), F3F(~2, ~0x35, ~0x0e2)|MCOND(~FCONDUGE), "9,f,g", 0, v9 }, +{ "fmovugeq", F3F(2, 0x35, 0x083)|MCOND(FCONDUGE), F3F(~2, ~0x35, ~0x083)|MCOND(~FCONDUGE), "6,f,g", 0, v9 }, +{ "fmovugeq", F3F(2, 0x35, 0x0a3)|MCOND(FCONDUGE), F3F(~2, ~0x35, ~0x0a3)|MCOND(~FCONDUGE), "7,f,g", 0, v9 }, +{ "fmovugeq", F3F(2, 0x35, 0x0c3)|MCOND(FCONDUGE), F3F(~2, ~0x35, ~0x0c3)|MCOND(~FCONDUGE), "8,f,g", 0, v9 }, +{ "fmovugeq", F3F(2, 0x35, 0x0e3)|MCOND(FCONDUGE), F3F(~2, ~0x35, ~0x0e3)|MCOND(~FCONDUGE), "9,f,g", 0, v9 }, +{ "fmovuges", F3F(2, 0x35, 0x081)|MCOND(FCONDUGE), F3F(~2, ~0x35, ~0x081)|MCOND(~FCONDUGE), "6,f,g", 0, v9 }, +{ "fmovuges", F3F(2, 0x35, 0x0a1)|MCOND(FCONDUGE), F3F(~2, ~0x35, ~0x0a1)|MCOND(~FCONDUGE), "7,f,g", 0, v9 }, +{ "fmovuges", F3F(2, 0x35, 0x0c1)|MCOND(FCONDUGE), F3F(~2, ~0x35, ~0x0c1)|MCOND(~FCONDUGE), "8,f,g", 0, v9 }, +{ "fmovuges", F3F(2, 0x35, 0x0e1)|MCOND(FCONDUGE), F3F(~2, ~0x35, ~0x0e1)|MCOND(~FCONDUGE), "9,f,g", 0, v9 }, +{ "fmovugq", F3F(2, 0x35, 0x083)|MCOND(FCONDUG), F3F(~2, ~0x35, ~0x083)|MCOND(~FCONDUG), "6,f,g", 0, v9 }, +{ "fmovugq", F3F(2, 0x35, 0x0a3)|MCOND(FCONDUG), F3F(~2, ~0x35, ~0x0a3)|MCOND(~FCONDUG), "7,f,g", 0, v9 }, +{ "fmovugq", F3F(2, 0x35, 0x0c3)|MCOND(FCONDUG), F3F(~2, ~0x35, ~0x0c3)|MCOND(~FCONDUG), "8,f,g", 0, v9 }, +{ "fmovugq", F3F(2, 0x35, 0x0e3)|MCOND(FCONDUG), F3F(~2, ~0x35, ~0x0e3)|MCOND(~FCONDUG), "9,f,g", 0, v9 }, +{ "fmovugs", F3F(2, 0x35, 0x081)|MCOND(FCONDUG), F3F(~2, ~0x35, ~0x081)|MCOND(~FCONDUG), "6,f,g", 0, v9 }, +{ "fmovugs", F3F(2, 0x35, 0x0a1)|MCOND(FCONDUG), F3F(~2, ~0x35, ~0x0a1)|MCOND(~FCONDUG), "7,f,g", 0, v9 }, +{ "fmovugs", F3F(2, 0x35, 0x0c1)|MCOND(FCONDUG), F3F(~2, ~0x35, ~0x0c1)|MCOND(~FCONDUG), "8,f,g", 0, v9 }, +{ "fmovugs", F3F(2, 0x35, 0x0e1)|MCOND(FCONDUG), F3F(~2, ~0x35, ~0x0e1)|MCOND(~FCONDUG), "9,f,g", 0, v9 }, +{ "fmovuld", F3F(2, 0x35, 0x082)|MCOND(FCONDUL), F3F(~2, ~0x35, ~0x082)|MCOND(~FCONDUL), "6,f,g", 0, v9 }, +{ "fmovuld", F3F(2, 0x35, 0x0a2)|MCOND(FCONDUL), F3F(~2, ~0x35, ~0x0a2)|MCOND(~FCONDUL), "7,f,g", 0, v9 }, +{ "fmovuld", F3F(2, 0x35, 0x0c2)|MCOND(FCONDUL), F3F(~2, ~0x35, ~0x0c2)|MCOND(~FCONDUL), "8,f,g", 0, v9 }, +{ "fmovuld", F3F(2, 0x35, 0x0e2)|MCOND(FCONDUL), F3F(~2, ~0x35, ~0x0e2)|MCOND(~FCONDUL), "9,f,g", 0, v9 }, +{ "fmovuled", F3F(2, 0x35, 0x082)|MCOND(FCONDULE), F3F(~2, ~0x35, ~0x082)|MCOND(~FCONDULE), "6,f,g", 0, v9 }, +{ "fmovuled", F3F(2, 0x35, 0x0a2)|MCOND(FCONDULE), F3F(~2, ~0x35, ~0x0a2)|MCOND(~FCONDULE), "7,f,g", 0, v9 }, +{ "fmovuled", F3F(2, 0x35, 0x0c2)|MCOND(FCONDULE), F3F(~2, ~0x35, ~0x0c2)|MCOND(~FCONDULE), "8,f,g", 0, v9 }, +{ "fmovuled", F3F(2, 0x35, 0x0e2)|MCOND(FCONDULE), F3F(~2, ~0x35, ~0x0e2)|MCOND(~FCONDULE), "9,f,g", 0, v9 }, +{ "fmovuleq", F3F(2, 0x35, 0x083)|MCOND(FCONDULE), F3F(~2, ~0x35, ~0x083)|MCOND(~FCONDULE), "6,f,g", 0, v9 }, +{ "fmovuleq", F3F(2, 0x35, 0x0a3)|MCOND(FCONDULE), F3F(~2, ~0x35, ~0x0a3)|MCOND(~FCONDULE), "7,f,g", 0, v9 }, +{ "fmovuleq", F3F(2, 0x35, 0x0c3)|MCOND(FCONDULE), F3F(~2, ~0x35, ~0x0c3)|MCOND(~FCONDULE), "8,f,g", 0, v9 }, +{ "fmovuleq", F3F(2, 0x35, 0x0e3)|MCOND(FCONDULE), F3F(~2, ~0x35, ~0x0e3)|MCOND(~FCONDULE), "9,f,g", 0, v9 }, +{ "fmovules", F3F(2, 0x35, 0x081)|MCOND(FCONDULE), F3F(~2, ~0x35, ~0x081)|MCOND(~FCONDULE), "6,f,g", 0, v9 }, +{ "fmovules", F3F(2, 0x35, 0x0a1)|MCOND(FCONDULE), F3F(~2, ~0x35, ~0x0a1)|MCOND(~FCONDULE), "7,f,g", 0, v9 }, +{ "fmovules", F3F(2, 0x35, 0x0c1)|MCOND(FCONDULE), F3F(~2, ~0x35, ~0x0c1)|MCOND(~FCONDULE), "8,f,g", 0, v9 }, +{ "fmovules", F3F(2, 0x35, 0x0e1)|MCOND(FCONDULE), F3F(~2, ~0x35, ~0x0e1)|MCOND(~FCONDULE), "9,f,g", 0, v9 }, +{ "fmovulq", F3F(2, 0x35, 0x083)|MCOND(FCONDUL), F3F(~2, ~0x35, ~0x083)|MCOND(~FCONDUL), "6,f,g", 0, v9 }, +{ "fmovulq", F3F(2, 0x35, 0x0a3)|MCOND(FCONDUL), F3F(~2, ~0x35, ~0x0a3)|MCOND(~FCONDUL), "7,f,g", 0, v9 }, +{ "fmovulq", F3F(2, 0x35, 0x0c3)|MCOND(FCONDUL), F3F(~2, ~0x35, ~0x0c3)|MCOND(~FCONDUL), "8,f,g", 0, v9 }, +{ "fmovulq", F3F(2, 0x35, 0x0e3)|MCOND(FCONDUL), F3F(~2, ~0x35, ~0x0e3)|MCOND(~FCONDUL), "9,f,g", 0, v9 }, +{ "fmovuls", F3F(2, 0x35, 0x081)|MCOND(FCONDUL), F3F(~2, ~0x35, ~0x081)|MCOND(~FCONDUL), "6,f,g", 0, v9 }, +{ "fmovuls", F3F(2, 0x35, 0x0a1)|MCOND(FCONDUL), F3F(~2, ~0x35, ~0x0a1)|MCOND(~FCONDUL), "7,f,g", 0, v9 }, +{ "fmovuls", F3F(2, 0x35, 0x0c1)|MCOND(FCONDUL), F3F(~2, ~0x35, ~0x0c1)|MCOND(~FCONDUL), "8,f,g", 0, v9 }, +{ "fmovuls", F3F(2, 0x35, 0x0e1)|MCOND(FCONDUL), F3F(~2, ~0x35, ~0x0e1)|MCOND(~FCONDUL), "9,f,g", 0, v9 }, +{ "fmovuq", F3F(2, 0x35, 0x083)|MCOND(FCONDU), F3F(~2, ~0x35, ~0x083)|MCOND(~FCONDU), "6,f,g", 0, v9 }, +{ "fmovuq", F3F(2, 0x35, 0x0a3)|MCOND(FCONDU), F3F(~2, ~0x35, ~0x0a3)|MCOND(~FCONDU), "7,f,g", 0, v9 }, +{ "fmovuq", F3F(2, 0x35, 0x0c3)|MCOND(FCONDU), F3F(~2, ~0x35, ~0x0c3)|MCOND(~FCONDU), "8,f,g", 0, v9 }, +{ "fmovuq", F3F(2, 0x35, 0x0e3)|MCOND(FCONDU), F3F(~2, ~0x35, ~0x0e3)|MCOND(~FCONDU), "9,f,g", 0, v9 }, +{ "fmovus", F3F(2, 0x35, 0x081)|MCOND(FCONDU), F3F(~2, ~0x35, ~0x081)|MCOND(~FCONDU), "6,f,g", 0, v9 }, +{ "fmovus", F3F(2, 0x35, 0x0a1)|MCOND(FCONDU), F3F(~2, ~0x35, ~0x0a1)|MCOND(~FCONDU), "7,f,g", 0, v9 }, +{ "fmovus", F3F(2, 0x35, 0x0c1)|MCOND(FCONDU), F3F(~2, ~0x35, ~0x0c1)|MCOND(~FCONDU), "8,f,g", 0, v9 }, +{ "fmovus", F3F(2, 0x35, 0x0e1)|MCOND(FCONDU), F3F(~2, ~0x35, ~0x0e1)|MCOND(~FCONDU), "9,f,g", 0, v9 }, +{ "fmovvcd", F3F(2, 0x35, 0x082)|MCOND(CONDVC), F3F(~2, ~0x35, ~0x082)|MCOND(~CONDVC), "z,f,g", 0, v9 }, +{ "fmovvcd", F3F(2, 0x35, 0x0a2)|MCOND(CONDVC), F3F(~2, ~0x35, ~0x0a2)|MCOND(~CONDVC), "Z,f,g", 0, v9 }, +{ "fmovvcq", F3F(2, 0x35, 0x083)|MCOND(CONDVC), F3F(~2, ~0x35, ~0x083)|MCOND(~CONDVC), "z,f,g", 0, v9 }, +{ "fmovvcq", F3F(2, 0x35, 0x0a3)|MCOND(CONDVC), F3F(~2, ~0x35, ~0x0a3)|MCOND(~CONDVC), "Z,f,g", 0, v9 }, +{ "fmovvcs", F3F(2, 0x35, 0x081)|MCOND(CONDVC), F3F(~2, ~0x35, ~0x081)|MCOND(~CONDVC), "z,f,g", 0, v9 }, +{ "fmovvcs", F3F(2, 0x35, 0x0a1)|MCOND(CONDVC), F3F(~2, ~0x35, ~0x0a1)|MCOND(~CONDVC), "Z,f,g", 0, v9 }, +{ "fmovvsd", F3F(2, 0x35, 0x082)|MCOND(CONDVS), F3F(~2, ~0x35, ~0x082)|MCOND(~CONDVS), "z,f,g", 0, v9 }, +{ "fmovvsd", F3F(2, 0x35, 0x0a2)|MCOND(CONDVS), F3F(~2, ~0x35, ~0x0a2)|MCOND(~CONDVS), "Z,f,g", 0, v9 }, +{ "fmovvsq", F3F(2, 0x35, 0x083)|MCOND(CONDVS), F3F(~2, ~0x35, ~0x083)|MCOND(~CONDVS), "z,f,g", 0, v9 }, +{ "fmovvsq", F3F(2, 0x35, 0x0a3)|MCOND(CONDVS), F3F(~2, ~0x35, ~0x0a3)|MCOND(~CONDVS), "Z,f,g", 0, v9 }, +{ "fmovvss", F3F(2, 0x35, 0x081)|MCOND(CONDVS), F3F(~2, ~0x35, ~0x081)|MCOND(~CONDVS), "z,f,g", 0, v9 }, +{ "fmovvss", F3F(2, 0x35, 0x0a1)|MCOND(CONDVS), F3F(~2, ~0x35, ~0x0a1)|MCOND(~CONDVS), "Z,f,g", 0, v9 }, +{ "fmovzd", F3F(2, 0x35, 0x082)|MCOND(CONDZ), F3F(~2, ~0x35, ~0x082)|MCOND(~CONDZ), "z,f,g", F_ALIAS, v9 }, +{ "fmovzd", F3F(2, 0x35, 0x082)|MCOND(FCONDZ), F3F(~2, ~0x35, ~0x082)|MCOND(~FCONDZ), "6,f,g", F_ALIAS, v9 }, +{ "fmovzd", F3F(2, 0x35, 0x0a2)|MCOND(CONDZ), F3F(~2, ~0x35, ~0x0a2)|MCOND(~CONDZ), "Z,f,g", F_ALIAS, v9 }, +{ "fmovzd", F3F(2, 0x35, 0x0a2)|MCOND(FCONDZ), F3F(~2, ~0x35, ~0x0a2)|MCOND(~FCONDZ), "7,f,g", F_ALIAS, v9 }, +{ "fmovzd", F3F(2, 0x35, 0x0c2)|MCOND(FCONDZ), F3F(~2, ~0x35, ~0x0c2)|MCOND(~FCONDZ), "8,f,g", F_ALIAS, v9 }, +{ "fmovzd", F3F(2, 0x35, 0x0e2)|MCOND(FCONDZ), F3F(~2, ~0x35, ~0x0e2)|MCOND(~FCONDZ), "9,f,g", F_ALIAS, v9 }, +{ "fmovzq", F3F(2, 0x35, 0x083)|MCOND(CONDZ), F3F(~2, ~0x35, ~0x083)|MCOND(~CONDZ), "z,f,g", F_ALIAS, v9 }, +{ "fmovzq", F3F(2, 0x35, 0x083)|MCOND(FCONDZ), F3F(~2, ~0x35, ~0x083)|MCOND(~FCONDZ), "6,f,g", F_ALIAS, v9 }, +{ "fmovzq", F3F(2, 0x35, 0x0a3)|MCOND(CONDZ), F3F(~2, ~0x35, ~0x0a3)|MCOND(~CONDZ), "Z,f,g", F_ALIAS, v9 }, +{ "fmovzq", F3F(2, 0x35, 0x0a3)|MCOND(FCONDZ), F3F(~2, ~0x35, ~0x0a3)|MCOND(~FCONDZ), "7,f,g", F_ALIAS, v9 }, +{ "fmovzq", F3F(2, 0x35, 0x0c3)|MCOND(FCONDZ), F3F(~2, ~0x35, ~0x0c3)|MCOND(~FCONDZ), "8,f,g", F_ALIAS, v9 }, +{ "fmovzq", F3F(2, 0x35, 0x0e3)|MCOND(FCONDZ), F3F(~2, ~0x35, ~0x0e3)|MCOND(~FCONDZ), "9,f,g", F_ALIAS, v9 }, +{ "fmovzs", F3F(2, 0x35, 0x081)|MCOND(CONDZ), F3F(~2, ~0x35, ~0x081)|MCOND(~CONDZ), "z,f,g", F_ALIAS, v9 }, +{ "fmovzs", F3F(2, 0x35, 0x081)|MCOND(FCONDZ), F3F(~2, ~0x35, ~0x081)|MCOND(~FCONDZ), "6,f,g", F_ALIAS, v9 }, +{ "fmovzs", F3F(2, 0x35, 0x0a1)|MCOND(CONDZ), F3F(~2, ~0x35, ~0x0a1)|MCOND(~CONDZ), "Z,f,g", F_ALIAS, v9 }, +{ "fmovzs", F3F(2, 0x35, 0x0a1)|MCOND(FCONDZ), F3F(~2, ~0x35, ~0x0a1)|MCOND(~FCONDZ), "7,f,g", F_ALIAS, v9 }, +{ "fmovzs", F3F(2, 0x35, 0x0c1)|MCOND(FCONDZ), F3F(~2, ~0x35, ~0x0c1)|MCOND(~FCONDZ), "8,f,g", F_ALIAS, v9 }, +{ "fmovzs", F3F(2, 0x35, 0x0e1)|MCOND(FCONDZ), F3F(~2, ~0x35, ~0x0e1)|MCOND(~FCONDZ), "9,f,g", F_ALIAS, v9 }, + +#define brfc(opcode, mask, lose) \ + { opcode, (mask), ANNUL|(lose), "l", F_DELAYED, v6 }, \ + { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED, v6 } + +#define brfcx(opcode, mask, lose) /* v9 */ \ + { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), "6,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a 6,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), "7,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a 7,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), "8,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a 8,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), "9,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a 9,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N9,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", F_DELAYED, v9 }, \ + { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", F_DELAYED, v9 } + +#define condfc(fop, cop, mask) \ + brfc(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask))), \ + brfcx(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask))), /* v9 */ \ + brfc(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask))) \ + +condfc("fb", "cb", 0x8), +condfc("fba", "cba", 0x8), +condfc("fbe", "cb0", 0x9), +condfc("fbg", "cb2", 0x6), +condfc("fbge", "cb02", 0xb), +condfc("fbl", "cb1", 0x4), +condfc("fble", "cb01", 0xd), +condfc("fblg", "cb12", 0x2), +condfc("fbn", "cbn", 0x0), +condfc("fbne", "cb123", 0x1), +condfc("fbo", "cb012", 0xf), +condfc("fbu", "cb3", 0x7), +condfc("fbue", "cb03", 0xa), +condfc("fbug", "cb23", 0x5), +condfc("fbuge", "cb023", 0xc), +condfc("fbul", "cb13", 0x3), +condfc("fbule", "cb013", 0xe), + +#undef condfc +#undef brfc + +{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */ +{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */ +{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */ +{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */ +{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */ + +{ "nop", F2(0, 4), F2(~0, ~4), "", 0, v6 }, /* sethi 0, %g0 */ + +{ "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "Sh,d", F_ALIAS, v6 }, + +{ "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 }, + +{ "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, v6 }, +{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, v6 }, +{ "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, v6 }, +{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, v6 }, + +{ "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, v6 }, +{ "tsubcctv", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "tsubcctv", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, v6 }, + +{ "unimp", F2(0x0, 0x0), 0xffffffff, "l", 0, v6 }, + +{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v6 }, +{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", 0, v6 }, +{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", 0, v6 }, +{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", 0, v6 }, + +{ "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, v6 }, +{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, v6 }, +{ "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, v6 }, +{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, v6 }, +{ "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, v6 }, +{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, v6 }, +{ "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, v6 }, +{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, v6 }, + +{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd */ +{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */ + +{ "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* xor rd,rs2,rd */ +{ "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, v6 }, /* xor rd,i,rd */ + +{ "fpop1", F3F(2, 0x34, 0), F3F(~2, ~0x34, ~1), "[1+2],d", 0, v6 }, +{ "fpop2", F3F(2, 0x35, 0), F3F(~2, ~0x35, ~1), "[1+2],d", 0, v6 }, + +/* float-start */ +{ "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", 0, v6 }, +{ "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", 0, v6 }, + + /* all of these conversions are confused and probably wrong. */ +{ "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", 0, v6 }, +{ "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", 0, v6 }, + +{ "fitox", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,g", 0, v6 }, /* collides in mneumonic with cypress */ + /* fitox collides in opf between cypress and v8, mneumonic between v6 and cypress */ +{ "fitox", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,g", 0, cypress }, /* collides */ +{ "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", 0, v8 }, /* collides in opf with cypress */ + +{ "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "f,J", 0, v9 }, + +{ "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", 0, v8 }, +{ "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", 0, v6 }, +{ "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", 0, v8 }, +{ "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", 0, v8 }, +{ "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", 0, v6 }, +{ "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", 0, v8 }, + +{ "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,g", 0, v9 }, + +{ "fxtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "f,g", 0, v7 }, /* these collide on the mneumonic */ +{ "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "f,g", 0, v9 }, +{ "fxtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "f,g", 0, cypress }, + +{ "fdtox", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,g", 0, cypress }, /* mneumonic collisions */ +{ "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,g", 0, v9 }, + +{ "fstox", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,g", 0, cypress }, +{ "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,g", 0, v9 }, + +{ "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", 0, v8 }, +{ "fxtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "f,g", 0, cypress }, + +{ "fxtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "f,H", 0, cypress }, /* collide in opf & mneumonic */ +{ "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "f,H", 0, v9 }, + +{ "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", 0, v6 }, +{ "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", 0, v8 }, +{ "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", 0, v6 }, +{ "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "e,f,g", 0, cypress }, +{ "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", 0, v6 }, +{ "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", 0, v8 }, +{ "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", 0, v6 }, +{ "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "e,f,g", 0, cypress }, + +{ "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", 0, v8 }, +{ "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", 0, v8 }, + +{ "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", 0, v7 }, +{ "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", 0, v8 }, +{ "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", 0, v7 }, +{ "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "f,g", 0, cypress }, + +{ "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", 0, v9 }, +{ "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", 0, v6 }, +{ "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", 0, v6 }, +{ "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", 0, v9 }, +{ "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", 0, v6 }, +{ "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", 0, v6 }, +{ "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", 0, v9 }, +{ "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", 0, v6 }, +{ "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", 0, v6 }, + +{ "popc", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|(0x3fff<<5), "2,d", 0, v9 }, + +{ "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", 0, v6 }, +{ "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", 0, v8 }, +{ "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", 0, v6 }, +{ "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "e,f,g", 0, cypress }, +{ "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", 0, v6 }, +{ "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", 0, v8 }, +{ "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", 0, v6 }, +{ "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "e,f,g", 0, cypress }, + +#define CMPFCC(x) (((x)&0x3)<<25) + +{ "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RS1_G0, "v,B", 0, v6 }, +{ "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", 0, v9 }, +{ "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", 0, v9 }, +{ "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", 0, v9 }, +{ "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", 0, v9 }, +{ "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RS1_G0, "v,B", 0, v6 }, +{ "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", 0, v9 }, +{ "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", 0, v9 }, +{ "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", 0, v9 }, +{ "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", 0, v9 }, +{ "fcmpeq", F3F(2, 0x34, 0x057), F3F(~2, ~0x34, ~0x057), "V,R,J", 0, v8 }, +{ "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", 0, v9 }, +{ "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", 0, v9 }, +{ "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", 0, v9 }, +{ "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", 0, v9 }, +{ "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RS1_G0, "e,f", 0, v6 }, +{ "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", 0, v9 }, +{ "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", 0, v9 }, +{ "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", 0, v9 }, +{ "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", 0, v9 }, +{ "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RS1_G0, "e,f", 0, cypress }, +{ "fcmpq", F3F(2, 0x34, 0x053), F3F(~2, ~0x34, ~0x053), "V,R,J", 0, v8 }, +{ "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", 0, v9 }, +{ "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", 0, v9 }, +{ "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", 0, v9 }, +{ "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", 0, v9 }, +{ "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RS1_G0, "e,f", 0, v6 }, +{ "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", 0, v9 }, +{ "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", 0, v9 }, +{ "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", 0, v9 }, +{ "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", 0, v9 }, +{ "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RS1_G0, "e,f", 0, cypress }, + +{ "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", 0, v6 }, +{ "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", 0, v6 }, + +{ "casx", F3(3, 0x0c, 1), F3(~3, ~0x0c, ~1), "[1],2,d", 0, v9 }, +{ "casxa", F3(3, 0x1c, 1), F3(~3, ~0x1c, ~1), "[1]A,2,d", 0, v9 }, +{ "cas", F3(3, 0x0c, 0), F3(~3, ~0x0c, ~0), "[1],2,d", 0, v9 }, +{ "casa", F3(3, 0x1c, 0), F3(~3, ~0x1c, ~0), "[1]A,2,d", 0, v9 }, + +{ "fmaddd", F3(2, 0x35, 0)|OPF_LOW(0xa), F3(~2, ~0x35, ~0)|OPF_LOW(~0xa), "v,B,u,H", 0, v9 }, +{ "fmaddq", F3(2, 0x35, 0)|OPF_LOW(0xb), F3(~2, ~0x35, ~0)|OPF_LOW(~0xb), "V,R,U,J", 0, v9 }, +{ "fmadds", F3(2, 0x35, 0)|OPF_LOW(0x9), F3(~2, ~0x35, ~0)|OPF_LOW(~0x9), "e,f,j,g", 0, v9 }, +{ "fmsubd", F3(2, 0x35, 0)|OPF_LOW(0xe), F3(~2, ~0x35, ~0)|OPF_LOW(~0xe), "v,B,u,H", 0, v9 }, +{ "fmsubq", F3(2, 0x35, 0)|OPF_LOW(0xf), F3(~2, ~0x35, ~0)|OPF_LOW(~0xf), "V,R,U,J", 0, v9 }, +{ "fmsubs", F3(2, 0x35, 0)|OPF_LOW(0xd), F3(~2, ~0x35, ~0)|OPF_LOW(~0xd), "e,f,j,g", 0, v9 }, + +}; + +#define NUMOPCODES ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0])) + +/* + * Local Variables: + * fill-column: 131 + * comment-column: 0 + * End: + */ + +/* end of sparc-opcode.h */ diff --git a/include/opcode/tahoe.h b/include/opcode/tahoe.h new file mode 100644 index 00000000000..b5cee249ee4 --- /dev/null +++ b/include/opcode/tahoe.h @@ -0,0 +1,213 @@ +/* + * Ported by the State University of New York at Buffalo by the Distributed + * Computer Systems Lab, Department of Computer Science, 1991. + */ + +#ifndef tahoe_opcodeT +#define tahoe_opcodeT int +#endif /* no tahoe_opcodeT */ + +struct vot_wot /* tahoe opcode table: wot to do with this */ + /* particular opcode */ +{ + char * args; /* how to compile said opcode */ + tahoe_opcodeT code; /* op-code (may be > 8 bits!) */ +}; + +struct vot /* tahoe opcode text */ +{ + char * name; /* opcode name: lowercase string [key] */ + struct vot_wot detail; /* rest of opcode table [datum] */ +}; + +#define vot_how args +#define vot_code code +#define vot_detail detail +#define vot_name name + +static struct vot +votstrs[] = +{ +{ "halt", {"", 0x00 } }, +{ "sinf", {"", 0x05 } }, +{ "ldf", {"rl", 0x06 } }, +{ "ldd", {"rq", 0x07 } }, +{ "addb2", {"rbmb", 0x08 } }, +{ "movb", {"rbwb", 0x09 } }, +{ "addw2", {"rwmw", 0x0a } }, +{ "movw", {"rwww", 0x0b } }, +{ "addl2", {"rlml", 0x0c } }, +{ "movl", {"rlwl", 0x0d } }, +{ "bbs", {"rlvlbw", 0x0e } }, +{ "nop", {"", 0x10 } }, +{ "brb", {"bb", 0x11 } }, +{ "brw", {"bw", 0x13 } }, +{ "cosf", {"", 0x15 } }, +{ "lnf", {"rl", 0x16 } }, +{ "lnd", {"rq", 0x17 } }, +{ "addb3", {"rbrbwb", 0x18 } }, +{ "cmpb", {"rbwb", 0x19 } }, +{ "addw3", {"rwrwww", 0x1a } }, +{ "cmpw", {"rwww", 0x1b } }, +{ "addl3", {"rlrlwl", 0x1c } }, +{ "cmpl", {"rlwl", 0x1d } }, +{ "bbc", {"rlvlbw", 0x1e } }, +{ "rei", {"", 0x20 } }, +{ "bneq", {"bb", 0x21 } }, +{ "bnequ", {"bb", 0x21 } }, +{ "cvtwl", {"rwwl", 0x23 } }, +{ "stf", {"wl", 0x26 } }, +{ "std", {"wq", 0x27 } }, +{ "subb2", {"rbmb", 0x28 } }, +{ "mcomb", {"rbwb", 0x29 } }, +{ "subw2", {"rwmw", 0x2a } }, +{ "mcomw", {"rwww", 0x2b } }, +{ "subl2", {"rlml", 0x2c } }, +{ "mcoml", {"rlwl", 0x2d } }, +{ "emul", {"rlrlrlwq", 0x2e } }, +{ "aoblss", {"rlmlbw", 0x2f } }, +{ "bpt", {"", 0x30 } }, +{ "beql", {"bb", 0x31 } }, +{ "beqlu", {"bb", 0x31 } }, +{ "cvtwb", {"rwwb", 0x33 } }, +{ "logf", {"", 0x35 } }, +{ "cmpf", {"rl", 0x36 } }, +{ "cmpd", {"rq", 0x37 } }, +{ "subb3", {"rbrbwb", 0x38 } }, +{ "bitb", {"rbrb", 0x39 } }, +{ "subw3", {"rwrwww", 0x3a } }, +{ "bitw", {"rwrw", 0x3b } }, +{ "subl3", {"rlrlwl", 0x3c } }, +{ "bitl", {"rlrl", 0x3d } }, +{ "ediv", {"rlrqwlwl", 0x3e } }, +{ "aobleq", {"rlmlbw", 0x3f } }, +{ "ret", {"", 0x40 } }, +{ "bgtr", {"bb", 0x41 } }, +{ "sqrtf", {"", 0x45 } }, +{ "cmpf2", {"rl", 0x46 } }, +{ "cmpd2", {"rqrq", 0x47 } }, +{ "shll", {"rbrlwl", 0x48 } }, +{ "clrb", {"wb", 0x49 } }, +{ "shlq", {"rbrqwq", 0x4a } }, +{ "clrw", {"ww", 0x4b } }, +{ "mull2", {"rlml", 0x4c } }, +{ "clrl", {"wl", 0x4d } }, +{ "shal", {"rbrlwl", 0x4e } }, +{ "bleq", {"bb", 0x51 } }, +{ "expf", {"", 0x55 } }, +{ "tstf", {"", 0x56 } }, +{ "tstd", {"", 0x57 } }, +{ "shrl", {"rbrlwl", 0x58 } }, +{ "tstb", {"rb", 0x59 } }, +{ "shrq", {"rbrqwq", 0x5a } }, +{ "tstw", {"rw", 0x5b } }, +{ "mull3", {"rlrlwl", 0x5c } }, +{ "tstl", {"rl", 0x5d } }, +{ "shar", {"rbrlwl", 0x5e } }, +{ "bbssi", {"rlmlbw", 0x5f } }, +{ "ldpctx", {"", 0x60 } }, +{ "pushd", {"", 0x67 } }, +{ "incb", {"mb", 0x69 } }, +{ "incw", {"mw", 0x6b } }, +{ "divl2", {"rlml", 0x6c } }, +{ "incl", {"ml", 0x6d } }, +{ "cvtlb", {"rlwb", 0x6f } }, +{ "svpctx", {"", 0x70 } }, +{ "jmp", {"ab", 0x71 } }, +{ "cvlf", {"rl", 0x76 } }, +{ "cvld", {"rl", 0x77 } }, +{ "decb", {"mb", 0x79 } }, +{ "decw", {"mw", 0x7b } }, +{ "divl3", {"rlrlwl", 0x7c } }, +{ "decl", {"ml", 0x7d } }, +{ "cvtlw", {"rlww", 0x7f } }, +{ "bgeq", {"bb", 0x81 } }, +{ "movs2", {"abab", 0x82 } }, +{ "cvfl", {"wl", 0x86 } }, +{ "cvdl", {"wl", 0x87 } }, +{ "orb2", {"rbmb", 0x88 } }, +{ "cvtbl", {"rbwl", 0x89 } }, +{ "orw2", {"rwmw", 0x8a } }, +{ "bispsw", {"rw", 0x8b } }, +{ "orl2", {"rlml", 0x8c } }, +{ "adwc", {"rlml", 0x8d } }, +{ "adda", {"rlml", 0x8e } }, +{ "blss", {"bb", 0x91 } }, +{ "cmps2", {"abab", 0x92 } }, +{ "ldfd", {"rl", 0x97 } }, +{ "orb3", {"rbrbwb", 0x98 } }, +{ "cvtbw", {"rbww", 0x99 } }, +{ "orw3", {"rwrwww", 0x9a } }, +{ "bicpsw", {"rw", 0x9b } }, +{ "orl3", {"rlrlwl", 0x9c } }, +{ "sbwc", {"rlml", 0x9d } }, +{ "suba", {"rlml", 0x9e } }, +{ "bgtru", {"bb", 0xa1 } }, +{ "cvdf", {"", 0xa6 } }, +{ "andb2", {"rbmb", 0xa8 } }, +{ "movzbl", {"rbwl", 0xa9 } }, +{ "andw2", {"rwmw", 0xaa } }, +{ "loadr", {"rwal", 0xab } }, +{ "andl2", {"rlml", 0xac } }, +{ "mtpr", {"rlrl", 0xad } }, +{ "ffs", {"rlwl", 0xae } }, +{ "blequ", {"bb", 0xb1 } }, +{ "negf", {"", 0xb6 } }, +{ "negd", {"", 0xb7 } }, +{ "andb3", {"rbrbwb", 0xb8 } }, +{ "movzbw", {"rbww", 0xb9 } }, +{ "andw3", {"rwrwww", 0xba } }, +{ "storer", {"rwal", 0xbb } }, +{ "andl3", {"rlrlwl", 0xbc } }, +{ "mfpr", {"rlwl", 0xbd } }, +{ "ffc", {"rlwl", 0xbe } }, +{ "calls", {"rbab", 0xbf } }, +{ "prober", {"rbabrl", 0xc0 } }, +{ "bvc", {"bb", 0xc1 } }, +{ "movs3", {"ababrw", 0xc2 } }, +{ "movzwl", {"rwwl", 0xc3 } }, +{ "addf", {"rl", 0xc6 } }, +{ "addd", {"rq", 0xc7 } }, +{ "xorb2", {"rbmb", 0xc8 } }, +{ "movob", {"rbwb", 0xc9 } }, +{ "xorw2", {"rwmw", 0xca } }, +{ "movow", {"rwww", 0xcb } }, +{ "xorl2", {"rlml", 0xcc } }, +{ "movpsl", {"wl", 0xcd } }, +{ "kcall", {"rw", 0xcf } }, +{ "probew", {"rbabrl", 0xd0 } }, +{ "bvs", {"bb", 0xd1 } }, +{ "cmps3", {"ababrw", 0xd2 } }, +{ "subf", {"rq", 0xd6 } }, +{ "subd", {"rq", 0xd7 } }, +{ "xorb3", {"rbrbwb", 0xd8 } }, +{ "pushb", {"rb", 0xd9 } }, +{ "xorw3", {"rwrwww", 0xda } }, +{ "pushw", {"rw", 0xdb } }, +{ "xorl3", {"rlrlwl", 0xdc } }, +{ "pushl", {"rl", 0xdd } }, +{ "insque", {"abab", 0xe0 } }, +{ "bcs", {"bb", 0xe1 } }, +{ "bgequ", {"bb", 0xe1 } }, +{ "mulf", {"rq", 0xe6 } }, +{ "muld", {"rq", 0xe7 } }, +{ "mnegb", {"rbwb", 0xe8 } }, +{ "movab", {"abwl", 0xe9 } }, +{ "mnegw", {"rwww", 0xea } }, +{ "movaw", {"awwl", 0xeb } }, +{ "mnegl", {"rlwl", 0xec } }, +{ "moval", {"alwl", 0xed } }, +{ "remque", {"ab", 0xf0 } }, +{ "bcc", {"bb", 0xf1 } }, +{ "blssu", {"bb", 0xf1 } }, +{ "divf", {"rq", 0xf6 } }, +{ "divd", {"rq", 0xf7 } }, +{ "movblk", {"alalrw", 0xf8 } }, +{ "pushab", {"ab", 0xf9 } }, +{ "pushaw", {"aw", 0xfb } }, +{ "casel", {"rlrlrl", 0xfc } }, +{ "pushal", {"al", 0xfd } }, +{ "callf", {"rbab", 0xfe } }, +{ "" , "" } /* empty is end sentinel */ + +}; diff --git a/include/opcode/vax.h b/include/opcode/vax.h new file mode 100644 index 00000000000..d604e3f9c65 --- /dev/null +++ b/include/opcode/vax.h @@ -0,0 +1,382 @@ +/* Vax opcde list. + Copyright (C) 1989, Free Software Foundation, Inc. + +This file is part of GDB and GAS. + +GDB and GAS are free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GDB and GAS are distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GDB or GAS; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#ifndef vax_opcodeT +#define vax_opcodeT int +#endif /* no vax_opcodeT */ + +struct vot_wot /* vax opcode table: wot to do with this */ + /* particular opcode */ +{ + char * args; /* how to compile said opcode */ + vax_opcodeT code; /* op-code (may be > 8 bits!) */ +}; + +struct vot /* vax opcode text */ +{ + char * name; /* opcode name: lowercase string [key] */ + struct vot_wot detail; /* rest of opcode table [datum] */ +}; + +#define vot_how args +#define vot_code code +#define vot_detail detail +#define vot_name name + +static const struct vot +votstrs[] = +{ +{ "halt", {"", 0x00 } }, +{ "nop", {"", 0x01 } }, +{ "rei", {"", 0x02 } }, +{ "bpt", {"", 0x03 } }, +{ "ret", {"", 0x04 } }, +{ "rsb", {"", 0x05 } }, +{ "ldpctx", {"", 0x06 } }, +{ "svpctx", {"", 0x07 } }, +{ "cvtps", {"rwabrwab", 0x08 } }, +{ "cvtsp", {"rwabrwab", 0x09 } }, +{ "index", {"rlrlrlrlrlwl", 0x0a } }, +{ "crc", {"abrlrwab", 0x0b } }, +{ "prober", {"rbrwab", 0x0c } }, +{ "probew", {"rbrwab", 0x0d } }, +{ "insque", {"abab", 0x0e } }, +{ "remque", {"abwl", 0x0f } }, +{ "bsbb", {"bb", 0x10 } }, +{ "brb", {"bb", 0x11 } }, +{ "bneq", {"bb", 0x12 } }, +{ "bnequ", {"bb", 0x12 } }, +{ "beql", {"bb", 0x13 } }, +{ "beqlu", {"bb", 0x13 } }, +{ "bgtr", {"bb", 0x14 } }, +{ "bleq", {"bb", 0x15 } }, +{ "jsb", {"ab", 0x16 } }, +{ "jmp", {"ab", 0x17 } }, +{ "bgeq", {"bb", 0x18 } }, +{ "blss", {"bb", 0x19 } }, +{ "bgtru", {"bb", 0x1a } }, +{ "blequ", {"bb", 0x1b } }, +{ "bvc", {"bb", 0x1c } }, +{ "bvs", {"bb", 0x1d } }, +{ "bcc", {"bb", 0x1e } }, +{ "bgequ", {"bb", 0x1e } }, +{ "blssu", {"bb", 0x1f } }, +{ "bcs", {"bb", 0x1f } }, +{ "addp4", {"rwabrwab", 0x20 } }, +{ "addp6", {"rwabrwabrwab", 0x21 } }, +{ "subp4", {"rwabrwab", 0x22 } }, +{ "subp6", {"rwabrwabrwab", 0x23 } }, +{ "cvtpt", {"rwababrwab", 0x24 } }, +{ "mulp", {"rwabrwabrwab", 0x25 } }, +{ "cvttp", {"rwababrwab", 0x26 } }, +{ "divp", {"rwabrwabrwab", 0x27 } }, +{ "movc3", {"rwabab", 0x28 } }, +{ "cmpc3", {"rwabab", 0x29 } }, +{ "scanc", {"rwababrb", 0x2a } }, +{ "spanc", {"rwababrb", 0x2b } }, +{ "movc5", {"rwabrbrwab", 0x2c } }, +{ "cmpc5", {"rwabrbrwab", 0x2d } }, +{ "movtc", {"rwabrbabrwab", 0x2e } }, +{ "movtuc", {"rwabrbabrwab", 0x2f } }, +{ "bsbw", {"bw", 0x30 } }, +{ "brw", {"bw", 0x31 } }, +{ "cvtwl", {"rwwl", 0x32 } }, +{ "cvtwb", {"rwwb", 0x33 } }, +{ "movp", {"rwabab", 0x34 } }, +{ "cmpp3", {"rwabab", 0x35 } }, +{ "cvtpl", {"rwabwl", 0x36 } }, +{ "cmpp4", {"rwabrwab", 0x37 } }, +{ "editpc", {"rwababab", 0x38 } }, +{ "matchc", {"rwabrwab", 0x39 } }, +{ "locc", {"rbrwab", 0x3a } }, +{ "skpc", {"rbrwab", 0x3b } }, +{ "movzwl", {"rwwl", 0x3c } }, +{ "acbw", {"rwrwmwbw", 0x3d } }, +{ "movaw", {"awwl", 0x3e } }, +{ "pushaw", {"aw", 0x3f } }, +{ "addf2", {"rfmf", 0x40 } }, +{ "addf3", {"rfrfwf", 0x41 } }, +{ "subf2", {"rfmf", 0x42 } }, +{ "subf3", {"rfrfwf", 0x43 } }, +{ "mulf2", {"rfmf", 0x44 } }, +{ "mulf3", {"rfrfwf", 0x45 } }, +{ "divf2", {"rfmf", 0x46 } }, +{ "divf3", {"rfrfwf", 0x47 } }, +{ "cvtfb", {"rfwb", 0x48 } }, +{ "cvtfw", {"rfww", 0x49 } }, +{ "cvtfl", {"rfwl", 0x4a } }, +{ "cvtrfl", {"rfwl", 0x4b } }, +{ "cvtbf", {"rbwf", 0x4c } }, +{ "cvtwf", {"rwwf", 0x4d } }, +{ "cvtlf", {"rlwf", 0x4e } }, +{ "acbf", {"rfrfmfbw", 0x4f } }, +{ "movf", {"rfwf", 0x50 } }, +{ "cmpf", {"rfrf", 0x51 } }, +{ "mnegf", {"rfwf", 0x52 } }, +{ "tstf", {"rf", 0x53 } }, +{ "emodf", {"rfrbrfwlwf", 0x54 } }, +{ "polyf", {"rfrwab", 0x55 } }, +{ "cvtfd", {"rfwd", 0x56 } }, + /* opcode 57 is not defined yet */ +{ "adawi", {"rwmw", 0x58 } }, + /* opcode 59 is not defined yet */ + /* opcode 5a is not defined yet */ + /* opcode 5b is not defined yet */ +{ "insqhi", {"abaq", 0x5c } }, +{ "insqti", {"abaq", 0x5d } }, +{ "remqhi", {"aqwl", 0x5e } }, +{ "remqti", {"aqwl", 0x5f } }, +{ "addd2", {"rdmd", 0x60 } }, +{ "addd3", {"rdrdwd", 0x61 } }, +{ "subd2", {"rdmd", 0x62 } }, +{ "subd3", {"rdrdwd", 0x63 } }, +{ "muld2", {"rdmd", 0x64 } }, +{ "muld3", {"rdrdwd", 0x65 } }, +{ "divd2", {"rdmd", 0x66 } }, +{ "divd3", {"rdrdwd", 0x67 } }, +{ "cvtdb", {"rdwb", 0x68 } }, +{ "cvtdw", {"rdww", 0x69 } }, +{ "cvtdl", {"rdwl", 0x6a } }, +{ "cvtrdl", {"rdwl", 0x6b } }, +{ "cvtbd", {"rbwd", 0x6c } }, +{ "cvtwd", {"rwwd", 0x6d } }, +{ "cvtld", {"rlwd", 0x6e } }, +{ "acbd", {"rdrdmdbw", 0x6f } }, +{ "movd", {"rdwd", 0x70 } }, +{ "cmpd", {"rdrd", 0x71 } }, +{ "mnegd", {"rdwd", 0x72 } }, +{ "tstd", {"rd", 0x73 } }, +{ "emodd", {"rdrbrdwlwd", 0x74 } }, +{ "polyd", {"rdrwab", 0x75 } }, +{ "cvtdf", {"rdwf", 0x76 } }, + /* opcode 77 is not defined yet */ +{ "ashl", {"rbrlwl", 0x78 } }, +{ "ashq", {"rbrqwq", 0x79 } }, +{ "emul", {"rlrlrlwq", 0x7a } }, +{ "ediv", {"rlrqwlwl", 0x7b } }, +{ "clrd", {"wd", 0x7c } }, +{ "clrg", {"wg", 0x7c } }, +{ "clrq", {"wd", 0x7c } }, +{ "movq", {"rqwq", 0x7d } }, +{ "movaq", {"aqwl", 0x7e } }, +{ "movad", {"adwl", 0x7e } }, +{ "pushaq", {"aq", 0x7f } }, +{ "pushad", {"ad", 0x7f } }, +{ "addb2", {"rbmb", 0x80 } }, +{ "addb3", {"rbrbwb", 0x81 } }, +{ "subb2", {"rbmb", 0x82 } }, +{ "subb3", {"rbrbwb", 0x83 } }, +{ "mulb2", {"rbmb", 0x84 } }, +{ "mulb3", {"rbrbwb", 0x85 } }, +{ "divb2", {"rbmb", 0x86 } }, +{ "divb3", {"rbrbwb", 0x87 } }, +{ "bisb2", {"rbmb", 0x88 } }, +{ "bisb3", {"rbrbwb", 0x89 } }, +{ "bicb2", {"rbmb", 0x8a } }, +{ "bicb3", {"rbrbwb", 0x8b } }, +{ "xorb2", {"rbmb", 0x8c } }, +{ "xorb3", {"rbrbwb", 0x8d } }, +{ "mnegb", {"rbwb", 0x8e } }, +{ "caseb", {"rbrbrb", 0x8f } }, +{ "movb", {"rbwb", 0x90 } }, +{ "cmpb", {"rbrb", 0x91 } }, +{ "mcomb", {"rbwb", 0x92 } }, +{ "bitb", {"rbrb", 0x93 } }, +{ "clrb", {"wb", 0x94 } }, +{ "tstb", {"rb", 0x95 } }, +{ "incb", {"mb", 0x96 } }, +{ "decb", {"mb", 0x97 } }, +{ "cvtbl", {"rbwl", 0x98 } }, +{ "cvtbw", {"rbww", 0x99 } }, +{ "movzbl", {"rbwl", 0x9a } }, +{ "movzbw", {"rbww", 0x9b } }, +{ "rotl", {"rbrlwl", 0x9c } }, +{ "acbb", {"rbrbmbbw", 0x9d } }, +{ "movab", {"abwl", 0x9e } }, +{ "pushab", {"ab", 0x9f } }, +{ "addw2", {"rwmw", 0xa0 } }, +{ "addw3", {"rwrwww", 0xa1 } }, +{ "subw2", {"rwmw", 0xa2 } }, +{ "subw3", {"rwrwww", 0xa3 } }, +{ "mulw2", {"rwmw", 0xa4 } }, +{ "mulw3", {"rwrwww", 0xa5 } }, +{ "divw2", {"rwmw", 0xa6 } }, +{ "divw3", {"rwrwww", 0xa7 } }, +{ "bisw2", {"rwmw", 0xa8 } }, +{ "bisw3", {"rwrwww", 0xa9 } }, +{ "bicw2", {"rwmw", 0xaa } }, +{ "bicw3", {"rwrwww", 0xab } }, +{ "xorw2", {"rwmw", 0xac } }, +{ "xorw3", {"rwrwww", 0xad } }, +{ "mnegw", {"rwww", 0xae } }, +{ "casew", {"rwrwrw", 0xaf } }, +{ "movw", {"rwww", 0xb0 } }, +{ "cmpw", {"rwrw", 0xb1 } }, +{ "mcomw", {"rwww", 0xb2 } }, +{ "bitw", {"rwrw", 0xb3 } }, +{ "clrw", {"ww", 0xb4 } }, +{ "tstw", {"rw", 0xb5 } }, +{ "incw", {"mw", 0xb6 } }, +{ "decw", {"mw", 0xb7 } }, +{ "bispsw", {"rw", 0xb8 } }, +{ "bicpsw", {"rw", 0xb9 } }, +{ "popr", {"rw", 0xba } }, +{ "pushr", {"rw", 0xbb } }, +{ "chmk", {"rw", 0xbc } }, +{ "chme", {"rw", 0xbd } }, +{ "chms", {"rw", 0xbe } }, +{ "chmu", {"rw", 0xbf } }, +{ "addl2", {"rlml", 0xc0 } }, +{ "addl3", {"rlrlwl", 0xc1 } }, +{ "subl2", {"rlml", 0xc2 } }, +{ "subl3", {"rlrlwl", 0xc3 } }, +{ "mull2", {"rlml", 0xc4 } }, +{ "mull3", {"rlrlwl", 0xc5 } }, +{ "divl2", {"rlml", 0xc6 } }, +{ "divl3", {"rlrlwl", 0xc7 } }, +{ "bisl2", {"rlml", 0xc8 } }, +{ "bisl3", {"rlrlwl", 0xc9 } }, +{ "bicl2", {"rlml", 0xca } }, +{ "bicl3", {"rlrlwl", 0xcb } }, +{ "xorl2", {"rlml", 0xcc } }, +{ "xorl3", {"rlrlwl", 0xcd } }, +{ "mnegl", {"rlwl", 0xce } }, +{ "casel", {"rlrlrl", 0xcf } }, +{ "movl", {"rlwl", 0xd0 } }, +{ "cmpl", {"rlrl", 0xd1 } }, +{ "mcoml", {"rlwl", 0xd2 } }, +{ "bitl", {"rlrl", 0xd3 } }, +{ "clrf", {"wf", 0xd4 } }, +{ "clrl", {"wl", 0xd4 } }, +{ "tstl", {"rl", 0xd5 } }, +{ "incl", {"ml", 0xd6 } }, +{ "decl", {"ml", 0xd7 } }, +{ "adwc", {"rlml", 0xd8 } }, +{ "sbwc", {"rlml", 0xd9 } }, +{ "mtpr", {"rlrl", 0xda } }, +{ "mfpr", {"rlwl", 0xdb } }, +{ "movpsl", {"wl", 0xdc } }, +{ "pushl", {"rl", 0xdd } }, +{ "moval", {"alwl", 0xde } }, +{ "movaf", {"afwl", 0xde } }, +{ "pushal", {"al", 0xdf } }, +{ "pushaf", {"af", 0xdf } }, +{ "bbs", {"rlabbb", 0xe0 } }, +{ "bbc", {"rlabbb", 0xe1 } }, +{ "bbss", {"rlabbb", 0xe2 } }, +{ "bbcs", {"rlabbb", 0xe3 } }, +{ "bbsc", {"rlabbb", 0xe4 } }, +{ "bbcc", {"rlabbb", 0xe5 } }, +{ "bbssi", {"rlabbb", 0xe6 } }, +{ "bbcci", {"rlabbb", 0xe7 } }, +{ "blbs", {"rlbb", 0xe8 } }, +{ "blbc", {"rlbb", 0xe9 } }, +{ "ffs", {"rlrbvbwl", 0xea } }, +{ "ffc", {"rlrbvbwl", 0xeb } }, +{ "cmpv", {"rlrbvbrl", 0xec } }, +{ "cmpzv", {"rlrbvbrl", 0xed } }, +{ "extv", {"rlrbvbwl", 0xee } }, +{ "extzv", {"rlrbvbwl", 0xef } }, +{ "insv", {"rlrlrbvb", 0xf0 } }, +{ "acbl", {"rlrlmlbw", 0xf1 } }, +{ "aoblss", {"rlmlbb", 0xf2 } }, +{ "aobleq", {"rlmlbb", 0xf3 } }, +{ "sobgeq", {"mlbb", 0xf4 } }, +{ "sobgtr", {"mlbb", 0xf5 } }, +{ "cvtlb", {"rlwb", 0xf6 } }, +{ "cvtlw", {"rlww", 0xf7 } }, +{ "ashp", {"rbrwabrbrwab", 0xf8 } }, +{ "cvtlp", {"rlrwab", 0xf9 } }, +{ "callg", {"abab", 0xfa } }, +{ "calls", {"rlab", 0xfb } }, +{ "xfc", {"", 0xfc } }, + /* undefined opcodes here */ +{ "cvtdh", {"rdwh", 0x32fd } }, +{ "cvtgf", {"rgwh", 0x33fd } }, +{ "addg2", {"rgmg", 0x40fd } }, +{ "addg3", {"rgrgwg", 0x41fd } }, +{ "subg2", {"rgmg", 0x42fd } }, +{ "subg3", {"rgrgwg", 0x43fd } }, +{ "mulg2", {"rgmg", 0x44fd } }, +{ "mulg3", {"rgrgwg", 0x45fd } }, +{ "divg2", {"rgmg", 0x46fd } }, +{ "divg3", {"rgrgwg", 0x47fd } }, +{ "cvtgb", {"rgwb", 0x48fd } }, +{ "cvtgw", {"rgww", 0x49fd } }, +{ "cvtgl", {"rgwl", 0x4afd } }, +{ "cvtrgl", {"rgwl", 0x4bfd } }, +{ "cvtbg", {"rbwg", 0x4cfd } }, +{ "cvtwg", {"rwwg", 0x4dfd } }, +{ "cvtlg", {"rlwg", 0x4efd } }, +{ "acbg", {"rgrgmgbw", 0x4ffd } }, +{ "movg", {"rgwg", 0x50fd } }, +{ "cmpg", {"rgrg", 0x51fd } }, +{ "mnegg", {"rgwg", 0x52fd } }, +{ "tstg", {"rg", 0x53fd } }, +{ "emodg", {"rgrwrgwlwg", 0x54fd } }, +{ "polyg", {"rgrwab", 0x55fd } }, +{ "cvtgh", {"rgwh", 0x56fd } }, + /* undefined opcodes here */ +{ "addh2", {"rhmh", 0x60fd } }, +{ "addh3", {"rhrhwh", 0x61fd } }, +{ "subh2", {"rhmh", 0x62fd } }, +{ "subh3", {"rhrhwh", 0x63fd } }, +{ "mulh2", {"rhmh", 0x64fd } }, +{ "mulh3", {"rhrhwh", 0x65fd } }, +{ "divh2", {"rhmh", 0x66fd } }, +{ "divh3", {"rhrhwh", 0x67fd } }, +{ "cvthb", {"rhwb", 0x68fd } }, +{ "cvthw", {"rhww", 0x69fd } }, +{ "cvthl", {"rhwl", 0x6afd } }, +{ "cvtrhl", {"rhwl", 0x6bfd } }, +{ "cvtbh", {"rbwh", 0x6cfd } }, +{ "cvtwh", {"rwwh", 0x6dfd } }, +{ "cvtlh", {"rlwh", 0x6efd } }, +{ "acbh", {"rhrhmhbw", 0x6ffd } }, +{ "movh", {"rhwh", 0x70fd } }, +{ "cmph", {"rhrh", 0x71fd } }, +{ "mnegh", {"rhwh", 0x72fd } }, +{ "tsth", {"rh", 0x73fd } }, +{ "emodh", {"rhrwrhwlwh", 0x74fd } }, +{ "polyh", {"rhrwab", 0x75fd } }, +{ "cvthg", {"rhwg", 0x76fd } }, + /* undefined opcodes here */ +{ "clrh", {"wh", 0x7cfd } }, +{ "clro", {"wo", 0x7cfd } }, +{ "movo", {"rowo", 0x7dfd } }, +{ "movah", {"ahwl", 0x7efd } }, +{ "movao", {"aowl", 0x7efd } }, +{ "pushah", {"ah", 0x7ffd } }, +{ "pushao", {"ao", 0x7ffd } }, + /* undefined opcodes here */ +{ "cvtfh", {"rfwh", 0x98fd } }, +{ "cvtfg", {"rfwg", 0x99fd } }, + /* undefined opcodes here */ +{ "cvthf", {"rhwf", 0xf6fd } }, +{ "cvthd", {"rhwd", 0xf7fd } }, + /* undefined opcodes here */ +{ "bugl", {"rl", 0xfdff } }, +{ "bugw", {"rw", 0xfeff } }, + /* undefined opcodes here */ + +{ "" , "" } /* empty is end sentinel */ + +}; /* votstrs */ + +/* end: vax.opcode.h */