From: Gabe Black <gabeblack@google.com>
Date: Wed, 6 Nov 2019 22:05:58 +0000 (-0800)
Subject: fastmodel: Implement the vecPredReg accessor functions.
X-Git-Tag: v19.0.0.0~141
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0233515ebf42bc235f1807dacfc919a11d97cbf2;p=gem5.git

fastmodel: Implement the vecPredReg accessor functions.

Change-Id: Iaf6f7d8d1db427bfd486e4bd43f67cc006751873
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23789
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
---

diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc b/src/arch/arm/fastmodel/iris/thread_context.cc
index e22b30059..b9d34e4bd 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -244,7 +244,8 @@ ThreadContext::ThreadContext(
         BaseCPU *cpu, int id, System *system, ::BaseTLB *dtb, ::BaseTLB *itb,
         iris::IrisConnectionInterface *iris_if, const std::string &iris_path) :
     _cpu(cpu), _threadId(id), _system(system), _dtb(dtb), _itb(itb),
-    _irisPath(iris_path), vecRegs(TheISA::NumVecRegs),
+    _irisPath(iris_path), vecRegs(ArmISA::NumVecRegs),
+    vecPredRegs(ArmISA::NumVecPredRegs),
     comInstEventQueue("instruction-based event queue"),
     client(iris_if, "client." + iris_path)
 {
@@ -545,4 +546,37 @@ ThreadContext::readVecRegFlat(RegIndex idx) const
     return readVecReg(RegId(VecRegClass, idx));
 }
 
+const ArmISA::VecPredRegContainer &
+ThreadContext::readVecPredReg(const RegId &reg_id) const
+{
+    RegIndex idx = reg_id.index();
+    if (idx >= vecPredRegIds.size())
+        return vecPredRegs.at(idx);
+
+    ArmISA::VecPredRegContainer &reg = vecPredRegs.at(idx);
+
+    iris::ResourceReadResult result;
+    call().resource_read(_instId, result, vecPredRegIds.at(idx));
+
+    size_t offset = 0;
+    size_t num_bits = reg.NUM_BITS;
+    uint8_t *bytes = (uint8_t *)result.data.data();
+    while (num_bits > 8) {
+        reg.set_bits(offset, 8, *bytes);
+        offset += 8;
+        num_bits -= 8;
+        bytes++;
+    }
+    if (num_bits)
+        reg.set_bits(offset, num_bits, *bytes);
+
+    return reg;
+}
+
+const ArmISA::VecPredRegContainer &
+ThreadContext::readVecPredRegFlat(RegIndex idx) const
+{
+    return readVecPredReg(RegId(VecPredRegClass, idx));
+}
+
 } // namespace Iris
diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh b/src/arch/arm/fastmodel/iris/thread_context.hh
index d7f1bdca8..77f3ec9fa 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -68,6 +68,7 @@ class ThreadContext : public ::ThreadContext
     // Temporary holding places for the vector reg accessors to return.
     // These are not updated live, only when requested.
     mutable std::vector<ArmISA::VecRegContainer> vecRegs;
+    mutable std::vector<ArmISA::VecPredRegContainer> vecPredRegs;
 
     Status _status = Active;
 
@@ -87,6 +88,7 @@ class ThreadContext : public ::ThreadContext
     iris::ResourceId icountRscId;
 
     ResourceIds vecRegIds;
+    ResourceIds vecPredRegIds;
 
     std::vector<iris::MemorySpaceInfo> memorySpaces;
     std::vector<iris::MemorySupportedAddressTranslationResult> translations;
@@ -374,11 +376,7 @@ class ThreadContext : public ::ThreadContext
         panic("%s not implemented.", __FUNCTION__);
     }
 
-    const VecPredRegContainer &
-    readVecPredReg(const RegId &reg) const override
-    {
-        panic("%s not implemented.", __FUNCTION__);
-    }
+    const VecPredRegContainer &readVecPredReg(const RegId &reg) const override;
     VecPredRegContainer &
     getWritableVecPredReg(const RegId &reg) override
     {
@@ -537,11 +535,7 @@ class ThreadContext : public ::ThreadContext
         panic("%s not implemented.", __FUNCTION__);
     }
 
-    const VecPredRegContainer &
-    readVecPredRegFlat(RegIndex idx) const override
-    {
-        panic("%s not implemented.", __FUNCTION__);
-    }
+    const VecPredRegContainer &readVecPredRegFlat(RegIndex idx) const override;
     VecPredRegContainer &
     getWritableVecPredRegFlat(RegIndex idx) override
     {