From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 13 Nov 2018 10:42:40 +0000 (+0000)
Subject: update requirements list, add discussion link
X-Git-Tag: convert-csv-opcode-to-binary~4846
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=024e607815b548a3b11a90666cc32ef2a55c1181;p=libreriscv.git

update requirements list, add discussion link
---

diff --git a/3d_gpu/microarchitecture.mdwn b/3d_gpu/microarchitecture.mdwn
index 1660e4b7b..0188ca18e 100644
--- a/3d_gpu/microarchitecture.mdwn
+++ b/3d_gpu/microarchitecture.mdwn
@@ -9,10 +9,12 @@
 * RV64GC compliance for running full GNU/Linux-based OS
 * SimpleV compliance
 * xBitManip (required for VPU and ideal for predication)
-* 4-lane 1Rx1W SRAMs for registers numbered 32 and above;
+* 4-lane 2Rx1W SRAMs for registers numbered 32 and above;
   Multi-R x Multi-W for registers 1-31.
   TODO: consider 2R for registers to be used as predication targets
   if >= 32.
+* Idea: generic implementation of ports on register file so as to be able
+  to experiment with different arrangements.
 * Potentially: Lane-swapping / crossing / data-multiplexing
   bus on register data (particularly because of SHAPE-REMAP (1D/2D/3D)
 * Potentially: Registers subdivided into 16-bit, to match
@@ -76,4 +78,4 @@ least-significant bits of the 7-bit register number.
 * <https://en.wikipedia.org/wiki/Tomasulo_algorithm>
 * <https://en.wikipedia.org/wiki/Reservation_station>
 * Register File Bank Cacheing <https://www.princeton.edu/~rblee/ELE572Papers/MultiBankRegFile_ISCA2000.pdf>
-
+* Discussion <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2018-November/000157.html>