From: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Sat, 13 Jan 2018 17:28:16 +0000 (-0500)
Subject: gm107/ir: change how SUQ works in preparation for bindless
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0255550eb13d665fe96bb6a3bcd3613e9de015c0;p=mesa.git

gm107/ir: change how SUQ works in preparation for bindless

All this information can be retrieved from the TIC directly. Avoid
having to dip into the constbuf information about the image.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
---

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
index 36e8ee95441..209f5c67ab0 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
@@ -262,6 +262,62 @@ GM107LoweringPass::handlePOPCNT(Instruction *i)
    return true;
 }
 
+bool
+GM107LoweringPass::handleSUQ(TexInstruction *suq)
+{
+   Value *ind = suq->getIndirectR();
+   Value *handle;
+   const int slot = suq->tex.r;
+   const int mask = suq->tex.mask;
+
+   if (suq->tex.bindless)
+      handle = ind;
+   else
+      handle = loadTexHandle(ind, slot + 32);
+
+   suq->tex.r = 0xff;
+   suq->tex.s = 0x1f;
+
+   suq->setIndirectR(NULL);
+   suq->setSrc(0, handle);
+   suq->tex.rIndirectSrc = 0;
+   suq->setSrc(1, bld.loadImm(NULL, 0));
+   suq->tex.query = TXQ_DIMS;
+   suq->op = OP_TXQ;
+
+   // We store CUBE / CUBE_ARRAY as a 2D ARRAY. Make sure that depth gets
+   // divided by 6.
+   if (mask & 0x4 && suq->tex.target.isCube()) {
+      int d = util_bitcount(mask & 0x3);
+      bld.setPosition(suq, true);
+      bld.mkOp2(OP_DIV, TYPE_U32, suq->getDef(d), suq->getDef(d),
+                bld.loadImm(NULL, 6));
+   }
+
+   // Samples come from a different query. If we want both samples and dims,
+   // create a second suq.
+   if (mask & 0x8) {
+      int d = util_bitcount(mask & 0x7);
+      Value *dst = suq->getDef(d);
+      TexInstruction *samples = suq;
+      assert(dst);
+
+      if (mask != 0x8) {
+         suq->setDef(d, NULL);
+         suq->tex.mask &= 0x7;
+         samples = cloneShallow(func, suq);
+         for (int i = 0; i < d; i++)
+            samples->setDef(d, NULL);
+         samples->setDef(0, dst);
+         suq->bb->insertAfter(suq, samples);
+      }
+      samples->tex.mask = 0x4;
+      samples->tex.query = TXQ_TYPE;
+   }
+
+   return true;
+}
+
 //
 // - add quadop dance for texturing
 // - put FP outputs in GPRs
@@ -283,6 +339,8 @@ GM107LoweringPass::visit(Instruction *i)
       return handleDFDX(i);
    case OP_POPCNT:
       return handlePOPCNT(i);
+   case OP_SUQ:
+      return handleSUQ(i->asTex());
    default:
       return NVC0LoweringPass::visit(i);
    }
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h
index d0737beda67..71e5ea6417a 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h
@@ -13,6 +13,7 @@ private:
    bool handleDFDX(Instruction *);
    bool handlePFETCH(Instruction *);
    bool handlePOPCNT(Instruction *);
+   bool handleSUQ(TexInstruction *);
 };
 
 class GM107LegalizeSSA : public NVC0LegalizeSSA
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
index 37d52976657..1b2b36d3cc9 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
@@ -136,7 +136,6 @@ private:
    Value *loadUboInfo64(Value *ptr, uint32_t off);
    Value *loadUboLength32(Value *ptr, uint32_t off);
    Value *loadMsInfo32(Value *ptr, uint32_t off);
-   Value *loadTexHandle(Value *ptr, unsigned int slot);
 
    void adjustCoordinatesMS(TexInstruction *);
    void processSurfaceCoordsGM107(TexInstruction *);
@@ -145,6 +144,8 @@ private:
    void convertSurfaceFormat(TexInstruction *);
 
 protected:
+   Value *loadTexHandle(Value *ptr, unsigned int slot);
+
    BuildUtil bld;
 
 private: