From: Nanley Chery <nanley.g.chery@intel.com>
Date: Wed, 6 Jul 2016 18:13:15 +0000 (-0700)
Subject: isl: Fix assert on raw buffer surface state size
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=028f6d8317f00a94b09df81e8f2cb944077e64a7;p=mesa.git

isl: Fix assert on raw buffer surface state size

See inline PRM reference.

Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
---

diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index fc7e1bae026..58e9af5f8ee 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -460,8 +460,15 @@ isl_genX(buffer_fill_state_s)(void *state,
    uint32_t num_elements = info->size / info->stride;
 
    if (GEN_GEN >= 7) {
+      /* From the IVB PRM, SURFACE_STATE::Height,
+       *
+       *    For typed buffer and structured buffer surfaces, the number
+       *    of entries in the buffer ranges from 1 to 2^27. For raw buffer
+       *    surfaces, the number of entries in the buffer is the number of bytes
+       *    which can range from 1 to 2^30.
+       */
       if (info->format == ISL_FORMAT_RAW) {
-         assert(num_elements <= (1ull << 31));
+         assert(num_elements <= (1ull << 30));
          assert((num_elements & 3) == 0);
       } else {
          assert(num_elements <= (1ull << 27));