From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 5 Aug 2009 09:59:25 +0000 (-0700)
Subject: X86: Make shifts/rotations that write to 32 bits of a register zero extend.
X-Git-Tag: Calvin_Submission~178
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=029d360db215ae081a2cba0b5552eaf77f509b20;p=gem5.git

X86: Make shifts/rotations that write to 32 bits of a register zero extend.
---

diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 447939abd..85fe8fe51 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -734,7 +734,7 @@ let {{
                 DestReg = merge(DestReg, top | bottom, dataSize);
             }
             else
-                DestReg = DestReg;
+                DestReg = merge(DestReg, DestReg, dataSize);
             '''
         flag_code = '''
             // If the shift amount is zero, no flags should be modified.
@@ -771,7 +771,7 @@ let {{
                 DestReg = merge(DestReg, top | bottom, dataSize);
             }
             else
-                DestReg = DestReg;
+                DestReg = merge(DestReg, DestReg, dataSize);
             '''
         flag_code = '''
             // If the shift amount is zero, no flags should be modified.
@@ -805,7 +805,7 @@ let {{
                 DestReg = merge(DestReg, top | bottom, dataSize);
             }
             else
-                DestReg = DestReg;
+                DestReg = merge(DestReg, DestReg, dataSize);
             '''
         flag_code = '''
             // If the shift amount is zero, no flags should be modified.
@@ -844,7 +844,7 @@ let {{
                 DestReg = merge(DestReg, top | bottom, dataSize);
             }
             else
-                DestReg = DestReg;
+                DestReg = merge(DestReg, DestReg, dataSize);
             '''
         flag_code = '''
             // If the shift amount is zero, no flags should be modified.